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from 97c025d2d8a PR target/88224: Fix FPU configuration of Cortex-R7 and Cortex-R8 new fbc08b62620 [AArch64][doc] Clarify -msve-vector-bits=128 behaviour

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Summary of changes: gcc/ChangeLog | 8 ++++++++ gcc/doc/invoke.texi | 23 +++++++++++++---------- 2 files changed, 21 insertions(+), 10 deletions(-)