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from 0be4fbeaa6a amdgcn: bug fix ldexp insn new 98ebdda3fd8 RISC-V: Fix simplify_ior_optimization.c on rv32 new a2d12abedc8 RISC-V: Fix wrong check of register occurrences [PR109535] new 9fde76a3be8 RISC-V: Fix riscv/arch-19.c with different ISA spec version

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Summary of changes: gcc/config/riscv/riscv-vsetvl.cc | 14 +- gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C | 144 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/arch-19.c | 4 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c | 11 ++ .../gcc.target/riscv/simplify_ior_optimization.c | 2 +- 5 files changed, 171 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c