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from bd6fa8c5b57 [AMDGPU] Call isLoopExiting for blocks in the loop. new 473e2ddc8eb [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP new 2b31edc15d8 [mips] Add missing schedinfo for atomic instructions new 46a23bad8cb [mips] Add missing schedinfo for MSA and ASE instructions new 6b9ac8abd2d GlobalISel: Add DAG compat for G_FCANONICALIZE new b68b21c025a GlobalISel: Add GINodeEquiv for min/max new bc712eaf908 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate new 23b47db4b09 AMDGPU/GlobalISel: Fix scc->vcc copy handling new b137067e347 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote new 2ab66137f5f AMDGPU/GlobalISel: RegBankSelect for WWM/WQM

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Summary of changes: .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 5 + lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 67 +++++--- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +- lib/Target/Mips/MipsDSPInstrInfo.td | 1 + lib/Target/Mips/MipsInstrInfo.td | 11 +- lib/Target/Mips/MipsMSAInstrInfo.td | 7 +- lib/Target/Mips/MipsScheduleP5600.td | 22 +++ .../AMDGPU/GlobalISel/inst-select-anyext.mir | 36 +++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 114 ++++++++++---- .../GlobalISel/inst-select-fcanonicalize.mir | 169 +++++++++++++++++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 39 +++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 83 ++++++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 83 ++++++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 83 ++++++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 83 ++++++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 48 +++++- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 31 ++++ ...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} | 10 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 31 ++++ 20 files changed, 870 insertions(+), 61 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir rename test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => regban [...] create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir