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from f5bddce9ea8 [RISCV] Add pseudo instruction for calls with explicit register new 067d3aa15ea [ARM] Handle fixup_arm_pcrel_9 correctly on big-endian targets

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Summary of changes: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 1 + test/MC/ARM/fixup-pcrel9.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 test/MC/ARM/fixup-pcrel9.s