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from 2061c51 [x86] add negate-i1 run for 32-bit target new a913b4a [LV] Account for predicated stores in instruction costs new 172d6c0 [ARM]: Assign cost of scaling used in addressing mode for ARM cores

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Summary of changes: lib/Target/ARM/ARM.td | 8 +++-- lib/Target/ARM/ARMISelLowering.cpp | 11 ++++++ lib/Target/ARM/ARMISelLowering.h | 8 +++++ lib/Target/ARM/ARMSubtarget.h | 4 +++ lib/Transforms/Vectorize/LoopVectorize.cpp | 6 ++++ test/CodeGen/ARM/lsr-scale-addr-mode.ll | 6 ++++ .../LoopVectorize/AArch64/predication_costs.ll | 40 +++++++++++++++++++++- 7 files changed, 80 insertions(+), 3 deletions(-)