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from d0a333612bf Use chain_next on eh_landing_pad_d for GTY (PR middle-end/110510) new 7c521f6751e RISC-V: Add support for vector crypto extensions

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 55 ++++++++++++++++++++++++++++++++ gcc/config/riscv/arch-canonicalize | 7 ++++ gcc/config/riscv/riscv-opts.h | 34 ++++++++++++++++++++ gcc/config/riscv/riscv.opt | 6 ++++ gcc/testsuite/gcc.target/riscv/zvbb.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvbc.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvkg.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvkn-1.c | 29 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvkn.c | 29 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvknc-1.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvknc-2.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvknc.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvkned.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvkng-1.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvkng-2.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvkng.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvknha.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvknhb.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvks-1.c | 29 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvks.c | 29 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksc-1.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksc-2.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksc.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksed.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvksg-1.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksg-2.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksg.c | 37 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zvksh.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zvkt.c | 13 ++++++++ 29 files changed, 779 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zvbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkg.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkn-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkn.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvknc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvknc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvknc.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkned.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkng-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkng-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkng.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvknha.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvknhb.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvks-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvks.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksc.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksed.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksg-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksg-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksg.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksh.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkt.c