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from 98b4425f4a2 [X86] Add a DAG combine to turn vzmovl+load into vzload if [...] new 7e88372346f [Peephole] Allow folding loads into instructions w/multiple [...] new e7815eaa374 [X86] Remove isel patterns that look for (vzext_movl (scala [...]
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Summary of changes: include/llvm/CodeGen/MachineRegisterInfo.h | 7 ++- lib/CodeGen/MachineRegisterInfo.cpp | 7 +++ lib/CodeGen/PeepholeOptimizer.cpp | 6 +- lib/Target/X86/X86InstrAVX512.td | 38 ------------- lib/Target/X86/X86InstrFragmentsSIMD.td | 7 --- lib/Target/X86/X86InstrSSE.td | 54 ------------------ test/CodeGen/X86/addr-mode-matcher-2.ll | 3 +- test/CodeGen/X86/or-branch.ll | 3 +- test/CodeGen/X86/peephole-fold-testrr.mir | 88 ++++++++++++++++++++++++++++++ test/CodeGen/X86/sibcall.ll | 6 +- test/CodeGen/X86/x86-shrink-wrapping.ll | 6 +- 11 files changed, 110 insertions(+), 115 deletions(-) create mode 100644 test/CodeGen/X86/peephole-fold-testrr.mir