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from fd2e2d7cc76 [X86] Add LODS schedule tests new 50b5493cd61 [Hexagon] Add support for Hexagon V65
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Summary of changes: include/llvm/BinaryFormat/ELF.h | 2 + include/llvm/IR/IntrinsicsHexagon.td | 953 ++- lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 288 +- lib/Target/Hexagon/CMakeLists.txt | 1 + .../Hexagon/Disassembler/HexagonDisassembler.cpp | 219 +- lib/Target/Hexagon/Hexagon.td | 77 +- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 25 +- lib/Target/Hexagon/HexagonDepArch.h | 10 +- lib/Target/Hexagon/HexagonDepArch.td | 7 +- lib/Target/Hexagon/HexagonDepDecoders.h | 78 + lib/Target/Hexagon/HexagonDepIICHVX.td | 722 +- lib/Target/Hexagon/HexagonDepIICScalar.td | 5242 ++++++++++----- lib/Target/Hexagon/HexagonDepITypes.h | 15 +- lib/Target/Hexagon/HexagonDepITypes.td | 15 +- lib/Target/Hexagon/HexagonDepInstrFormats.td | 822 ++- lib/Target/Hexagon/HexagonDepInstrInfo.td | 7067 ++++++++++++-------- lib/Target/Hexagon/HexagonDepMappings.td | 849 +-- lib/Target/Hexagon/HexagonDepOperands.td | 11 +- lib/Target/Hexagon/HexagonDepTimingClasses.h | 168 +- lib/Target/Hexagon/HexagonFrameLowering.cpp | 19 +- lib/Target/Hexagon/HexagonGatherPacketize.cpp | 103 + lib/Target/Hexagon/HexagonIICHVX.td | 12 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 27 + lib/Target/Hexagon/HexagonISelDAGToDAG.h | 3 + lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 121 + lib/Target/Hexagon/HexagonISelLowering.cpp | 38 + lib/Target/Hexagon/HexagonISelLowering.h | 3 + lib/Target/Hexagon/HexagonInstrFormats.td | 34 +- lib/Target/Hexagon/HexagonInstrFormatsV65.td | 32 + lib/Target/Hexagon/HexagonInstrInfo.cpp | 182 +- lib/Target/Hexagon/HexagonInstrInfo.h | 15 +- lib/Target/Hexagon/HexagonIntrinsics.td | 27 + lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td | 86 + lib/Target/Hexagon/HexagonPatternsV65.td | 70 + lib/Target/Hexagon/HexagonRegisterInfo.cpp | 2 + lib/Target/Hexagon/HexagonRegisterInfo.td | 59 +- lib/Target/Hexagon/HexagonSchedule.td | 5 + lib/Target/Hexagon/HexagonScheduleV65.td | 40 + lib/Target/Hexagon/HexagonSubtarget.cpp | 8 +- lib/Target/Hexagon/HexagonSubtarget.h | 9 + lib/Target/Hexagon/HexagonTargetMachine.cpp | 9 +- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 100 +- lib/Target/Hexagon/HexagonVLIWPacketizer.h | 9 + .../Hexagon/MCTargetDesc/HexagonAsmBackend.cpp | 5 +- lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 19 +- .../Hexagon/MCTargetDesc/HexagonMCChecker.cpp | 322 +- lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h | 51 +- .../Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp | 6 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 114 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 30 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 175 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.h | 6 +- .../Hexagon/MCTargetDesc/HexagonShuffler.cpp | 212 +- lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h | 9 + .../Hexagon/intrinsics/v65-gather-double.ll | 60 + test/CodeGen/Hexagon/intrinsics/v65-gather.ll | 59 + .../Hexagon/intrinsics/v65-scatter-double.ll | 78 + .../Hexagon/intrinsics/v65-scatter-gather.ll | 32 + test/CodeGen/Hexagon/intrinsics/v65-scatter.ll | 78 + test/CodeGen/Hexagon/intrinsics/v65.ll | 156 + test/CodeGen/Hexagon/livephysregs-lane-masks.mir | 2 +- test/MC/Hexagon/PacketRules/endloop_branches.s | 13 +- test/MC/Hexagon/hvx-double-implies-hvx.s | 4 + test/MC/Hexagon/new-value-check.s | 29 +- test/MC/Hexagon/v60-misc.s | 2 +- test/MC/Hexagon/v65_all.s | 184 + test/MC/Hexagon/vpred_defs.s | 9 + test/MC/Hexagon/vscatter-slot.s | 25 + test/MC/Hexagon/vtmp_def.s | 5 + 69 files changed, 13364 insertions(+), 5905 deletions(-) create mode 100644 lib/Target/Hexagon/HexagonDepDecoders.h create mode 100644 lib/Target/Hexagon/HexagonGatherPacketize.cpp create mode 100644 lib/Target/Hexagon/HexagonInstrFormatsV65.td create mode 100644 lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td create mode 100644 lib/Target/Hexagon/HexagonPatternsV65.td create mode 100644 lib/Target/Hexagon/HexagonScheduleV65.td create mode 100644 test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll create mode 100644 test/CodeGen/Hexagon/intrinsics/v65-gather.ll create mode 100644 test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll create mode 100644 test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll create mode 100644 test/CodeGen/Hexagon/intrinsics/v65-scatter.ll create mode 100644 test/CodeGen/Hexagon/intrinsics/v65.ll create mode 100644 test/MC/Hexagon/hvx-double-implies-hvx.s create mode 100644 test/MC/Hexagon/v65_all.s create mode 100644 test/MC/Hexagon/vpred_defs.s create mode 100644 test/MC/Hexagon/vscatter-slot.s create mode 100644 test/MC/Hexagon/vtmp_def.s