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from e8511cbba69 Docs: Add vector register constarint for asm operands new 1133cfab472 aarch64: PR target/99195 annotate simple floating-point pat [...] new 12fae1f7fbe aarch64: PR target/99195 annotate HADDSUB patterns for vec- [...]
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Summary of changes: gcc/config/aarch64/aarch64-simd.md | 20 ++++++++-------- gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c | 27 +++++++++++++++++----- .../aarch64/simd/{pr99195_1.c => pr99195_2.c} | 26 +++++++++------------ 3 files changed, 42 insertions(+), 31 deletions(-) copy gcc/testsuite/gcc.target/aarch64/simd/{pr99195_1.c => pr99195_2.c} (71%)