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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-aarch64-build_cross in repository toolchain/ci/binutils-gdb.
from 4488e43c49 sim: rx: scope the unique configure flag adds e27c0d7ae3 Automatic date update in version.in adds 1b40d569a8 sim: cris: clean up printf & abort usage a bit adds 61e2dde2db gdb/python: handle saving user registers in a frame unwinder adds 8b9c48b287 gdb/python: move PyLong_From* calls into py-utils.c adds d52b800721 gdb/python: add PendingFrame.level and Frame.level methods adds 96f842cbdb gdb/riscv: add support for vector registers in target descriptions adds b4ee29a445 Automatic date update in version.in adds be0387eed0 sim: hw: rework configure option & device selection adds 456ef1c1d4 sim: unify hardware settings adds ded5cb9444 picojava assembler and disassembler fixes adds 46b8b3d6f8 opcodes: make use of __builtin_popcount when available adds 80dc83fd0e gdb/remote: handle target dying just before a stepi adds 50331d64f1 RISC-V: Clarify the addends of pc-relative access. adds e5b771060e [gdb/testsuite] Add gdb.dwarf2/imported-unit-c.exp adds 80d1206d7f gdb: Support DW_LLE_start_end new 4e317a765b gdb/python: print name of unwinder that claimed frame in deb [...]
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: bfd/ChangeLog | 17 ++ bfd/elfnn-riscv.c | 160 +++++++----- bfd/version.h | 2 +- gas/ChangeLog | 9 + gas/config/tc-pj.c | 5 +- gas/testsuite/gas/pj/ops.d | 284 ++++++++++----------- gas/testsuite/gas/pj/ops.s | 34 +-- gdb/ChangeLog | 56 ++++ gdb/NEWS | 11 + gdb/arch/riscv.c | 6 + gdb/arch/riscv.h | 12 +- gdb/breakpoint.c | 8 + gdb/doc/ChangeLog | 10 + gdb/doc/gdb.texinfo | 8 + gdb/doc/python.texi | 9 + gdb/dwarf2/loc.c | 20 +- gdb/python/lib/gdb/__init__.py | 14 +- gdb/python/py-frame.c | 23 ++ gdb/python/py-inferior.c | 2 +- gdb/python/py-unwind.c | 76 +++++- gdb/riscv-tdep.c | 121 ++++++++- gdb/riscv-tdep.h | 8 +- gdb/testsuite/ChangeLog | 32 +++ gdb/testsuite/gdb.dwarf2/imported-unit-c.exp | 110 ++++++++ ...oclists-multiple-cus.c => loclists-start-end.c} | 0 gdb/testsuite/gdb.dwarf2/loclists-start-end.exp | 137 ++++++++++ gdb/testsuite/gdb.python/py-frame.exp | 11 + gdb/testsuite/gdb.python/py-pending-frame-level.c | 49 ++++ .../gdb.python/py-pending-frame-level.exp | 65 +++++ gdb/testsuite/gdb.python/py-pending-frame-level.py | 55 ++++ gdb/testsuite/gdb.python/py-unwind-user-regs.c | 37 +++ gdb/testsuite/gdb.python/py-unwind-user-regs.exp | 98 +++++++ gdb/testsuite/gdb.python/py-unwind-user-regs.py | 72 ++++++ gdb/testsuite/gdb.server/server-kill.exp | 65 ++++- gdb/testsuite/lib/dwarf.exp | 29 +++ ld/ChangeLog | 14 + ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 3 + ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld | 13 + ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d | 18 ++ ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s | 21 ++ ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d | 4 + ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s | 13 + ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d | 4 + ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s | 13 + opcodes/ChangeLog | 10 + opcodes/cgen-dis.c | 4 + opcodes/pj-dis.c | 5 +- sim/ChangeLog | 16 ++ sim/Makefile.in | 3 + sim/README-HACKING | 4 +- sim/aarch64/ChangeLog | 9 + sim/aarch64/aclocal.m4 | 1 - sim/aarch64/configure | 67 +---- sim/aclocal.m4 | 1 + sim/arch-subdir.mk.in | 5 + sim/arm/ChangeLog | 9 + sim/arm/aclocal.m4 | 1 - sim/arm/configure | 67 +---- sim/avr/ChangeLog | 9 + sim/avr/aclocal.m4 | 1 - sim/avr/configure | 67 +---- sim/bfin/ChangeLog | 11 + sim/bfin/Makefile.in | 33 +++ sim/bfin/aclocal.m4 | 1 - sim/bfin/configure | 92 ------- sim/bfin/configure.ac | 33 --- sim/bpf/ChangeLog | 9 + sim/bpf/aclocal.m4 | 1 - sim/bpf/configure | 60 ----- sim/common/ChangeLog | 11 + sim/common/Make-common.in | 9 +- sim/configure | 54 +++- sim/configure.ac | 1 + sim/cr16/ChangeLog | 9 + sim/cr16/aclocal.m4 | 1 - sim/cr16/configure | 67 +---- sim/cris/ChangeLog | 17 ++ sim/cris/Makefile.in | 2 + sim/cris/aclocal.m4 | 1 - sim/cris/configure | 60 ----- sim/cris/configure.ac | 1 - sim/cris/traps.c | 77 +++--- sim/d10v/ChangeLog | 9 + sim/d10v/aclocal.m4 | 1 - sim/d10v/configure | 67 +---- sim/erc32/ChangeLog | 9 + sim/erc32/aclocal.m4 | 1 - sim/erc32/configure | 67 +---- sim/example-synacor/ChangeLog | 9 + sim/example-synacor/aclocal.m4 | 1 - sim/example-synacor/configure | 67 +---- sim/frv/ChangeLog | 9 + sim/frv/aclocal.m4 | 1 - sim/frv/configure | 60 ----- sim/ft32/ChangeLog | 9 + sim/ft32/aclocal.m4 | 1 - sim/ft32/configure | 67 +---- sim/h8300/ChangeLog | 9 + sim/h8300/aclocal.m4 | 1 - sim/h8300/configure | 67 +---- sim/iq2000/ChangeLog | 9 + sim/iq2000/aclocal.m4 | 1 - sim/iq2000/configure | 60 ----- sim/lm32/ChangeLog | 11 + sim/lm32/Makefile.in | 2 + sim/lm32/aclocal.m4 | 1 - sim/lm32/configure | 60 ----- sim/lm32/configure.ac | 1 - sim/m32c/ChangeLog | 9 + sim/m32c/aclocal.m4 | 1 - sim/m32c/configure | 67 +---- sim/m32r/ChangeLog | 11 + sim/m32r/Makefile.in | 2 + sim/m32r/aclocal.m4 | 1 - sim/m32r/configure | 61 ----- sim/m32r/configure.ac | 2 - sim/m4/sim_ac_option_hardware.m4 | 48 +--- sim/m4/sim_ac_output.m4 | 5 - sim/m68hc11/ChangeLog | 11 + sim/m68hc11/Makefile.in | 2 + sim/m68hc11/aclocal.m4 | 1 - sim/m68hc11/configure | 69 +---- sim/m68hc11/configure.ac | 4 - sim/mcore/ChangeLog | 9 + sim/mcore/aclocal.m4 | 1 - sim/mcore/configure | 67 +---- sim/microblaze/ChangeLog | 9 + sim/microblaze/aclocal.m4 | 1 - sim/microblaze/configure | 67 +---- sim/mips/ChangeLog | 11 + sim/mips/Makefile.in | 1 + sim/mips/aclocal.m4 | 1 - sim/mips/configure | 63 ----- sim/mips/configure.ac | 4 - sim/mn10300/ChangeLog | 11 + sim/mn10300/Makefile.in | 2 + sim/mn10300/aclocal.m4 | 1 - sim/mn10300/configure | 60 ----- sim/mn10300/configure.ac | 1 - sim/moxie/ChangeLog | 9 + sim/moxie/aclocal.m4 | 1 - sim/moxie/configure | 67 +---- sim/msp430/ChangeLog | 9 + sim/msp430/aclocal.m4 | 1 - sim/msp430/configure | 67 +---- sim/or1k/ChangeLog | 9 + sim/or1k/aclocal.m4 | 1 - sim/or1k/configure | 60 ----- sim/pru/ChangeLog | 9 + sim/pru/aclocal.m4 | 1 - sim/pru/configure | 67 +---- sim/riscv/ChangeLog | 9 + sim/riscv/aclocal.m4 | 1 - sim/riscv/configure | 60 ----- sim/rl78/ChangeLog | 9 + sim/rl78/aclocal.m4 | 1 - sim/rl78/configure | 67 +---- sim/rx/ChangeLog | 9 + sim/rx/aclocal.m4 | 1 - sim/rx/configure | 62 +---- sim/sh/ChangeLog | 9 + sim/sh/aclocal.m4 | 1 - sim/sh/configure | 67 +---- sim/v850/ChangeLog | 9 + sim/v850/aclocal.m4 | 1 - sim/v850/configure | 60 ----- 166 files changed, 2007 insertions(+), 2450 deletions(-) create mode 100644 gdb/testsuite/gdb.dwarf2/imported-unit-c.exp copy gdb/testsuite/gdb.dwarf2/{loclists-multiple-cus.c => loclists-start-end.c} (100%) create mode 100644 gdb/testsuite/gdb.dwarf2/loclists-start-end.exp create mode 100644 gdb/testsuite/gdb.python/py-pending-frame-level.c create mode 100644 gdb/testsuite/gdb.python/py-pending-frame-level.exp create mode 100644 gdb/testsuite/gdb.python/py-pending-frame-level.py create mode 100644 gdb/testsuite/gdb.python/py-unwind-user-regs.c create mode 100644 gdb/testsuite/gdb.python/py-unwind-user-regs.exp create mode 100644 gdb/testsuite/gdb.python/py-unwind-user-regs.py create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d create mode 100644 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s