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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-O3 in repository toolchain/ci/llvm-project.
from 23d08271a4b2 Add cmake/ to release tarballs via concatenation adds 22d7bee01a5a [PPCISelLowering] Avoid emitting calls to __multi3, __muloti4 adds db07d9f098b3 [MC] Fix llvm_unreachable when a STB_GNU_UNIQUE symbol nee [...] adds a4681df0202c [libcxx] [test] Avoid spurious test breakage in clang-cl-d [...] adds e9b26b5b2a70 [RISCV] Add test case for miscompile caused by treating AN [...] adds 5b9dd016bec7 [SelectionDAG][RISCV] Make RegsForValue::getCopyToRegs exp [...] adds c9ec4902c3e3 [llvm-objdump][test] dos2unix some files adds 1007cb795a3c [llvm-objdump] --private-headers: change errors to warning [...] adds 311a622edd31 [Object][test] Fix invalid.test adds 353068233f21 [ELF] Fix llvm_unreachable failure when COMMON is placed i [...] adds 67a290460c37 [VectorCombine] Insert addrspacecast when crossing address [...] adds d53e2603383a [AArch64] Allow .variant_pcs before the symbol is registered adds fd98b0f1a6a1 [SelectionDAG] Don't create illegally-typed nodes while co [...] adds d150523f0776 [AArch64] Use correct calling convention for each vararg adds aaf0c921a54a [clang-repl] Add an accessor to our underlying execution engine adds ec13fed5867f [X86] lowerV8I16Shuffle - use explicit SmallVector<SDValue [...] adds d4e3c50b2bda [libc++] Define `namespace views` in its own detail header. adds 8475349bd639 [AARCH64] ssbs should be enabled by default for cortex-x1, [...] adds 6697c5bc3a1e [compiler-rt] [scudo] Use -mcrc32 on x86 when available adds c62053979489 [AArch64] Fix the upper limit for folded address offsets for COFF adds 5c9eed741dbd [libc++] Make __dir_stream visibility declaration consistent adds 87599bdabbd1 [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file adds b6e91d4a331e [RISCV] Pre-commit for fixing stack offset for RVV object adds d0f27fb44952 [RISCV] Fixing stack offset for RVV object with vararg in stack. adds 2c4d288eae8b [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/ adds fe8a27acd716 [LV] Handle zero cost loops in selectInterleaveCount. adds 5ea5e3c01b7b [InstCombine] add tests for low-mask of ashr; NFC adds 43ee392dd462 [InstCombine] try to fold low-mask of ashr to lshr adds 8c3445ac1c8b [AArch64][LOH] Don't ignore regmasks in bundles by iterati [...] adds d800180f6bee [lld][COFF] Fix TypeServerSource lookup on GUID collisions adds e11b929a3c97 [LLD][COFF] Fix TypeServerSource matcher with more than on [...] adds 46d19f3a8699 [CMake] Use CMAKE_SYSROOT to build libs for Win to ARM cro [...] adds b6dbee34387d [CMake] Update cache file for Win to ARM cross tooolchain. NFC. adds 6c41c8edb0cc [CMake] Replace `TARGET_TRIPLE` with `TOOLCHAIN_TARGET_TRI [...] adds 3400d0293a14 [CMake] Update cache file for Win to ARM Linux cross toolc [...] adds 33504b3bbe10 [PowerPC] Allow absolute expressions in relocations adds 09fba23d41f7 [compiler-rt] Implement __clear_cache on FreeBSD/powerpc adds e8f03f2057ee Force GHashCell to be 8-byte-aligned. adds 0f56ce0fb207 [DebugInfo][InstrRef] Avoid a crash from mixed variable lo [...] adds 571c7d8f6dae Reland "[llvm][AArch64] Insert "bti j" after call to setjmp" adds 0fbe860711be [Clang][Fortify] drop inline decls when redeclared adds b83c4a2dc0fb [x86] Fix infinite loop inside DAG combiner with lzcnt feature. adds 9a3e81e1f91f [InstCombine] canonicalize select with signbit test adds e7a9fd4f57d6 [LV] Add test case for PR54427. adds 0d2efbb8b82c [LV] Always use add to add scalar iv and (startidx + step) [...] adds ebf29ba9f0a3 [LV] Remove stray debug dump added in 0d2efbb8b82c. adds 324127d8da95 [libcxx] Add some missing xlocale wrapper functions for OpenBSD adds dc30b0d3320d [ELF] --emit-relocs: fix missing STT_SECTION when the firs [...] adds 50c6ba751fa2 [RISCV] Only try LUI+SH*ADD+ADDI for int materialization i [...] adds 58d5fbe2c20b [llvm-mt] Add support /notify_update adds 21ce6cfd1d93 [RISCV] Add tests showing incorrect BUILD_VECTOR lowering adds 9efcce92b55b [RISCV] Fix lowering of BUILD_VECTORs as VID sequences adds e19be4195b87 [RISCV] Add another test showing incorrect BUILD_VECTOR lowering adds 1f4c7b2a9120 [RISCV] Don't emit fractional VIDs with negative steps adds a36801750327 [asan] Always skip first object from dl_iterate_phdr adds 0e27d08cdeb3 [RISCV] Fix crash for section alignment with .option norvc
No new revisions were added by this update.
Summary of changes: clang/cmake/caches/CrossWinToARMLinux.cmake | 175 ++-- clang/docs/ClangCommandLineReference.rst | 2 +- clang/docs/ReleaseNotes.rst | 6 +- clang/include/clang/Driver/Options.td | 2 +- clang/include/clang/Interpreter/Interpreter.h | 2 + clang/lib/CodeGen/CGExpr.cpp | 14 +- clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 3 + clang/lib/Interpreter/IncrementalExecutor.h | 1 + clang/lib/Interpreter/Interpreter.cpp | 6 + .../CodeGen/fread-inline-builtin-late-redecl.c | 26 + clang/test/Driver/aarch64-ssbs.c | 4 + clang/test/Preprocessor/aarch64-target-features.c | 2 +- compiler-rt/cmake/config-ix.cmake | 1 + compiler-rt/lib/asan/asan_linux.cpp | 30 +- compiler-rt/lib/builtins/clear_cache.c | 5 +- compiler-rt/lib/scudo/CMakeLists.txt | 7 +- compiler-rt/lib/scudo/scudo_allocator.cpp | 4 +- compiler-rt/lib/scudo/scudo_crc32.cpp | 4 +- compiler-rt/lib/scudo/scudo_crc32.h | 12 +- compiler-rt/lib/scudo/standalone/CMakeLists.txt | 7 +- compiler-rt/lib/scudo/standalone/checksum.h | 8 +- compiler-rt/lib/scudo/standalone/chunk.h | 4 +- compiler-rt/lib/scudo/standalone/crc32_hw.cpp | 4 +- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__filesystem/directory_entry.h | 2 +- libcxx/include/__ranges/views.h | 35 + libcxx/include/__support/openbsd/xlocale.h | 20 + libcxx/include/module.modulemap | 1 + libcxx/include/ranges | 11 +- .../detail.headers/ranges/views.module.verify.cpp} | 16 +- .../pointer.volatile.pass.cpp | 16 +- lld/COFF/DebugTypes.cpp | 19 +- lld/ELF/SyntheticSections.h | 4 +- lld/ELF/Writer.cpp | 41 +- .../pdb-type-server-guid-collision-a-pdb.yaml | 1018 ++++++++++++++++++++ .../Inputs/pdb-type-server-guid-collision-a.yaml | 171 ++++ .../pdb-type-server-guid-collision-b-pdb.yaml | 1018 ++++++++++++++++++++ .../Inputs/pdb-type-server-guid-collision-b.yaml | 171 ++++ .../pdb-type-server-guid-collision-invalid.test | 26 + .../COFF/pdb-type-server-guid-collision-valid.test | 17 + lld/test/ELF/emit-relocs-synthetic.s | 54 ++ lld/test/ELF/linkerscript/common.s | 75 +- llvm/include/llvm/CodeGen/FastISel.h | 7 + llvm/include/llvm/CodeGen/SelectionDAG.h | 13 + llvm/include/llvm/CodeGen/SelectionDAGISel.h | 1 + llvm/lib/CodeGen/MachineFunction.cpp | 3 - llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | 3 +- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 3 +- .../CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 3 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 10 +- llvm/lib/MC/ELFObjectWriter.cpp | 1 + llvm/lib/Object/ELF.cpp | 2 - llvm/lib/Support/AArch64TargetParser.cpp | 2 + llvm/lib/Target/AArch64/AArch64.td | 12 +- llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 2 +- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 34 + llvm/lib/Target/AArch64/AArch64FastISel.cpp | 8 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 163 ++-- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 9 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 11 + llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 + .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 16 +- .../Target/AArch64/GISel/AArch64CallLowering.cpp | 12 +- .../AArch64/GISel/AArch64PreLegalizerCombiner.cpp | 7 +- .../AArch64/MCTargetDesc/AArch64ELFStreamer.cpp | 1 + llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 63 +- .../Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 2 + .../PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp | 2 + .../Target/PowerPC/MCTargetDesc/PPCFixupKinds.h | 4 + .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 4 +- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp | 13 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 + llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 +- llvm/lib/Target/RISCV/CMakeLists.txt | 1 + .../Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 8 +- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 54 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 23 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 71 +- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp | 30 + llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h | 25 + llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 23 + llvm/lib/Target/RISCV/RISCVTargetMachine.h | 8 + llvm/lib/Target/X86/X86ISelLowering.cpp | 24 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 6 + .../Transforms/InstCombine/InstCombineSelect.cpp | 17 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 37 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 8 +- llvm/test/CodeGen/AArch64/darwinpcs-tail.ll | 36 + llvm/test/CodeGen/AArch64/fold-global-offsets.ll | 16 +- llvm/test/CodeGen/AArch64/loh.mir | 9 + .../CodeGen/AArch64/setjmp-bti-no-enforcement.ll | 51 + llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll | 83 ++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 55 ++ .../CostModel => CodeGen/MIR}/RISCV/lit.local.cfg | 0 .../CodeGen/MIR/RISCV/machine-function-info.mir | 138 +++ .../PowerPC/overflow-intrinsic-optimizations.ll | 12 + .../PowerPC/umulo-128-legalisation-lowering.ll | 169 ++-- .../CodeGen/PowerPC/urem-seteq-illegal-types.ll | 61 +- llvm/test/CodeGen/RISCV/aext-to-sext.ll | 39 + llvm/test/CodeGen/RISCV/imm.ll | 36 + .../CodeGen/RISCV/rvv/constant-folding-crash.ll | 85 ++ .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 37 + .../rvv/wrong-stack-offset-for-rvv-object.mir | 220 +++++ llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll | 34 + llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll | 117 +++ llvm/test/MC/AArch64/directive-variant_pcs-err.s | 3 - llvm/test/MC/AArch64/directive-variant_pcs.s | 42 +- llvm/test/MC/ELF/gnu-unique.s | 11 +- llvm/test/MC/PowerPC/ppc64-abs-reloc.s | 22 + llvm/test/MC/RISCV/align-option-relax.s | 8 + llvm/test/MC/RISCV/align.s | 8 + llvm/test/Object/invalid.test | 5 +- llvm/test/Transforms/InstCombine/and.ll | 90 +- llvm/test/Transforms/InstCombine/ashr-lshr.ll | 80 +- llvm/test/Transforms/InstCombine/logical-select.ll | 4 +- .../Transforms/InstCombine/truncating-saturate.ll | 4 +- ...-select-interleave-count-loop-with-cost-zero.ll | 50 + .../LoopVectorize/induction-unroll-novec.ll | 46 + .../AMDGPU/as-transition-inseltpoison.ll | 4 +- .../VectorCombine/AMDGPU/as-transition.ll | 4 +- .../VectorCombine/X86/load-inseltpoison.ll | 17 + llvm/test/tools/llvm-mt/notify_update.test | 16 + .../tools/llvm-objdump/ELF/dynamic-malformed.test | 38 + llvm/test/tools/llvm-objdump/ELF/invalid-phdr.test | 5 +- .../tools/llvm-objdump/ELF/private-headers.test | 130 +-- .../tools/llvm-objdump/ELF/program-headers.test | 649 ++++++------- llvm/tools/llvm-mt/Opts.td | 2 +- llvm/tools/llvm-mt/llvm-mt.cpp | 25 +- llvm/tools/llvm-objdump/ELFDump.cpp | 8 +- 133 files changed, 5229 insertions(+), 1069 deletions(-) create mode 100644 clang/test/CodeGen/fread-inline-builtin-late-redecl.c create mode 100644 libcxx/include/__ranges/views.h copy libcxx/{include/__support/openbsd/xlocale.h => test/libcxx/diagnostics/detail [...] create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-a-pdb.yaml create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-a.yaml create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-b-pdb.yaml create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-b.yaml create mode 100644 lld/test/COFF/pdb-type-server-guid-collision-invalid.test create mode 100644 lld/test/COFF/pdb-type-server-guid-collision-valid.test create mode 100644 lld/test/ELF/emit-relocs-synthetic.s create mode 100644 llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp create mode 100644 llvm/test/CodeGen/AArch64/darwinpcs-tail.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti.ll copy llvm/test/{Analysis/CostModel => CodeGen/MIR}/RISCV/lit.local.cfg (100%) create mode 100644 llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir create mode 100644 llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir create mode 100644 llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll create mode 100644 llvm/test/MC/PowerPC/ppc64-abs-reloc.s create mode 100644 llvm/test/MC/RISCV/align-option-relax.s create mode 100644 llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleav [...] create mode 100644 llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll create mode 100644 llvm/test/tools/llvm-mt/notify_update.test create mode 100644 llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test