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from 962c2a67ea8 AMDGPU/GlobalISel: Implement select for 32-bit G_ADD new a1ebca4b3e7 [docs][llvm-readelf] Expand llvm-readelf documentation new 8d62be14dc5 AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane new 60235d0ed6b [X86] Add widenSubVector to size in bits helper. NFCI.
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Summary of changes: .../{llvm-readobj.rst => llvm-readelf.rst} | 231 +++++++-------------- docs/CommandGuide/llvm-readobj.rst | 24 +++ lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 75 +++++++ lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 7 + lib/Target/X86/X86ISelLowering.cpp | 20 +- ....mir => regbankselect-amdgcn.readfirstlane.mir} | 17 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 71 +++++++ 7 files changed, 274 insertions(+), 171 deletions(-) copy docs/CommandGuide/{llvm-readobj.rst => llvm-readelf.rst} (57%) copy test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn.wwm.mir => regbankselect [...] create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir