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from 046501dc30f veclower: Don't ICE on .VEC_CONVERT calls with no lhs [PR96426] new e5907f3b631 aarch64: Add missing clobber for fjcvtzs new 50703e93a82 aarch64: New Straight Line Speculation (SLS) mitigation flags new 6a356af5603 aarch64: Introduce SLS mitigation for RET and BR instructions new 20be37acba1 aarch64: Mitigate SLS for BLR instruction
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Summary of changes: gcc/config/aarch64/aarch64-protos.h | 5 + gcc/config/aarch64/aarch64.c | 342 ++++++++++++++++++++- gcc/config/aarch64/aarch64.h | 25 +- gcc/config/aarch64/aarch64.md | 90 ++++-- gcc/config/aarch64/aarch64.opt | 4 + gcc/config/aarch64/constraints.md | 9 + gcc/config/aarch64/predicates.md | 3 +- gcc/doc/invoke.texi | 12 + gcc/doc/sourcebuild.texi | 3 + gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c | 33 ++ .../aarch64/sls-mitigation/sls-miti-blr-bti.c | 40 +++ .../aarch64/sls-mitigation/sls-miti-blr.c | 33 ++ .../aarch64/sls-mitigation/sls-miti-retbr-pacret.c | 21 ++ .../aarch64/sls-mitigation/sls-miti-retbr.c | 119 +++++++ .../aarch64/sls-mitigation/sls-mitigation.exp | 73 +++++ gcc/testsuite/lib/target-supports.exp | 23 +- 16 files changed, 800 insertions(+), 35 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-miti-blr-bti.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-miti-blr.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-miti-retbr- [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-miti-retbr.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-mitigation.exp