[Tcwg-commits] [gcc] branch master updated (dc3f70adc3a -> dd8ee1df28e)

20 May 2025


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unknown user pushed a change to branch master
in repository gcc.
from  dc3f70adc3a Daily bump.
       new  4a8ce14a581 RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost
       new  7c5c12b938e RISC-V: Add test for vec_duplicate + vrsub.vv combine case  [...]
       new  e604b48288b RISC-V: Add test for vec_duplicate + vrsub.vv combine case  [...]
       new  7e12feefb45 RISC-V: Add test for vec_duplicate + vrsub.vv combine case  [...]
       new  82de5c5c139 RISC-V: Add test for vec_duplicate + vrsub.vv combine case  [...]
       new  a05beea2b87 RISC-V: Add test for vec_duplicate + vrsub.vv combine case  [...]
       new  d1697f3d685 RISC-V: Add test for vec_duplicate + vrsub.vv combine case  [...]
       new  dd8ee1df28e RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]
The 8 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/autovec-opt.md                    |  16 +-
 gcc/config/riscv/riscv-protos.h                    |   2 +
 gcc/config/riscv/riscv-v.cc                        |  49 +++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c  |   9 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c   |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h |  63 ++++
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h       | 392 +++++++++++++++++++++
 .../{vx_vadd-run-1-i16.c => vx_vrsub-run-1-i16.c}  |   6 +-
 .../{vx_vadd-run-1-i32.c => vx_vrsub-run-1-i32.c}  |   6 +-
 .../{vx_vadd-run-1-i64.c => vx_vrsub-run-1-i64.c}  |   6 +-
 .../{vx_vsub-run-1-i8.c => vx_vrsub-run-1-i8.c}    |   6 +-
 .../{vx_vadd-run-1-u16.c => vx_vrsub-run-1-u16.c}  |   6 +-
 .../{vx_vadd-run-1-u32.c => vx_vrsub-run-1-u32.c}  |   6 +-
 .../{vx_vadd-run-1-u64.c => vx_vrsub-run-1-u64.c}  |   6 +-
 .../{vx_vadd-run-1-u8.c => vx_vrsub-run-1-u8.c}    |   6 +-
 61 files changed, 826 insertions(+), 129 deletions(-)
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-i16.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-i32.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-i64.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vsub-run-1-i8.c => vx_vr [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u16.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u32.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u64.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u8.c => vx_vr [...]
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[Tcwg-commits] [gcc] branch master updated (dc3f70adc3a -> dd8ee1df28e)