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from bed61b5646f RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t new e0600a02fc3 RISC-V: Add RVV comparison autovectorization
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Summary of changes: gcc/config/riscv/autovec.md | 112 +++++++++ gcc/config/riscv/riscv-protos.h | 9 + gcc/config/riscv/riscv-v.cc | 255 +++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/cmp/vcond-1.c | 157 +++++++++++++ .../rvv/autovec/cmp/vcond-2.c} | 41 ++-- .../gcc.target/riscv/rvv/autovec/cmp/vcond-3.c | 13 ++ .../rvv/autovec/cmp/vcond_run-1.c} | 6 +- .../rvv/autovec/cmp/vcond_run-2.c} | 8 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c | 6 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + 10 files changed, 580 insertions(+), 29 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c copy gcc/testsuite/gcc.target/{aarch64/sve/vcond_4_sel.c => riscv/rvv/autovec/cmp/ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c copy gcc/testsuite/gcc.target/{aarch64/sve/vcond_2_run.c => riscv/rvv/autovec/cmp/ [...] copy gcc/testsuite/gcc.target/{aarch64/sve/vcond_4_run.c => riscv/rvv/autovec/cmp/ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c