[Tcwg-commits] [gcc] branch master updated (2a37a4a3cbf -> edfc4402504)

10 Feb 2023


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unknown user pushed a change to branch master
in repository gcc.
from  2a37a4a3cbf Revert "docs: add caveat for __builtin_cpu_supports"
       new  dc87e1391c5 tree-optimization/108724 - vectorized code getting piecewis [...]
       new  a035d133809 RISC-V: Add binary vx C/C++ support
       new  649107f6d1f RISC-V: Add vmul.vv C API tests
       new  1b0bd520f5a RISC-V: Add vmul.vv C++ API tests
       new  e9d5e4ac357 RISC-V: Add vxor.vx C API tests
       new  fe9e2eccb9e RISC-V: Add vsub.vx C API tests
       new  d2d6b0915e0 RISC-V: Add vrsub.vx C API tests
       new  b65e8a19002 RISC-V: Add vremu.vx C API tests
       new  dc4d66d543b RISC-V: Add vrem.vx C API tests
       new  76cd8e80058 RISC-V: Add vor.vx C API tests
       new  ac843ce70e6 RISC-V: Add vmul.vx C API tests
       new  f82338eca2f RISC-V: Add vminu.vx C API tests
       new  5255664d4ab RISC-V: Add vmin.vx C API tests
       new  a524f0c44f1 RISC-V: Add vmaxu.vx C API tests
       new  e6a085499cb RISC-V: Add vmax.vx C API tests
       new  8f1320e0976 RISC-V: Add vdivu C API tests
       new  5442df6cbdf RISC-V: Add vdiv.vx C API tests
       new  9f35eb5d51b RISC-V: Add vand.vx C API tests
       new  f7bff05f5e9 RISC-V: Add vadd.vx C API tests
       new  ce4b00f393b RISC-V: Add binary op vx constraint tests
       new  7d8c4a59fdf RISC-V: Add vxor.vx C++ API tests
       new  525274d82f3 RISC-V: Add vsub.vx C++ API tests
       new  f0cd94672fc RISC-V: Add vrsub.vx C++ API tests
       new  1e6324f7f36 RISC-V: Add vadd.vx C++ API tests
       new  d862fd1832a RISC-V: Add vremu.vx C++ API tests.
       new  988cc529af6 RISC-V: Add vrem.vx C++ API tests
       new  6289b83ffe2 RISC-V: Add vor.vx C++ API tests
       new  8c971d59a7c RISC-V: Add vmul.vx C++ API testcase
       new  679ba598453 RISC-V: Add vminu.vx C++ API tests
       new  0e5ae1fad00 RISC-V: Add vmin.vx C++ API tests
       new  66979d72eb9 RISC-V: Add vmaxu.vx C++ API tests.
       new  ae3ea1340de RISC-V: Add vmax.vx C++ API tests.
       new  8189380d868 RISC-V: Add vdivu.vx C++ API tests
       new  e0e32c3397e RISC-V: Add vdiv.vx C++ API test.
       new  edfc4402504 RISC-V: Add vand.vx C++ API test.
The 35 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/constraints.md                    |  17 +-
 gcc/config/riscv/predicates.md                     |  16 +-
 gcc/config/riscv/riscv-protos.h                    |   8 +-
 gcc/config/riscv/riscv-v.cc                        |  90 +++-
 gcc/config/riscv/riscv-vector-builtins-bases.cc    |  16 +-
 gcc/config/riscv/riscv-vector-builtins-bases.h     |   1 +
 .../riscv/riscv-vector-builtins-functions.def      |  31 +-
 gcc/config/riscv/riscv-vector-builtins.cc          |  51 ++
 gcc/config/riscv/riscv.h                           |   2 +-
 gcc/config/riscv/vector-iterators.md               |  37 +-
 gcc/config/riscv/vector.md                         | 366 ++++++++++++-
 .../base/{vadd_vv_mu-1.C => vadd_vx_mu_rv32-1.C}   | 129 +++--
 .../base/{vadd_vv_mu-2.C => vadd_vx_mu_rv32-2.C}   | 129 +++--
 .../base/{vadd_vv_mu-3.C => vadd_vx_mu_rv32-3.C}   | 129 +++--
 .../base/{vadd_vv_mu-1.C => vadd_vx_mu_rv64-1.C}   | 134 ++---
 .../base/{vadd_vv_mu-2.C => vadd_vx_mu_rv64-2.C}   | 134 ++---
 .../base/{vadd_vv_mu-3.C => vadd_vx_mu_rv64-3.C}   | 134 ++---
 .../g++.target/riscv/rvv/base/vadd_vx_rv32-1.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vadd_vx_rv32-2.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vadd_vx_rv32-3.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vadd_vx_rv64-1.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vadd_vx_rv64-2.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vadd_vx_rv64-3.C     | 578 +++++++++++++++++++++
 .../base/{vadd_vv_tu-1.C => vadd_vx_tu_rv32-1.C}   | 129 +++--
 .../base/{vadd_vv_tu-2.C => vadd_vx_tu_rv32-2.C}   | 129 +++--
 .../base/{vadd_vv_tu-3.C => vadd_vx_tu_rv32-3.C}   | 129 +++--
 .../base/{vadd_vv_tu-1.C => vadd_vx_tu_rv64-1.C}   | 134 ++---
 .../base/{vadd_vv_tu-2.C => vadd_vx_tu_rv64-2.C}   | 134 ++---
 .../base/{vadd_vv_tu-3.C => vadd_vx_tu_rv64-3.C}   | 134 ++---
 .../base/{vadd_vv_tum-1.C => vadd_vx_tum_rv32-1.C} | 129 +++--
 .../base/{vadd_vv_tum-2.C => vadd_vx_tum_rv32-2.C} | 129 +++--
 .../base/{vadd_vv_tum-3.C => vadd_vx_tum_rv32-3.C} | 129 +++--
 .../base/{vadd_vv_tum-1.C => vadd_vx_tum_rv64-1.C} | 134 ++---
 .../base/{vadd_vv_tum-2.C => vadd_vx_tum_rv64-2.C} | 134 ++---
 .../base/{vadd_vv_tum-3.C => vadd_vx_tum_rv64-3.C} | 134 ++---
 .../{vadd_vv_tumu-1.C => vadd_vx_tumu_rv32-1.C}    | 129 +++--
 .../{vadd_vv_tumu-2.C => vadd_vx_tumu_rv32-2.C}    | 129 +++--
 .../{vadd_vv_tumu-3.C => vadd_vx_tumu_rv32-3.C}    | 129 +++--
 .../{vadd_vv_tumu-1.C => vadd_vx_tumu_rv64-1.C}    | 134 ++---
 .../{vadd_vv_tumu-2.C => vadd_vx_tumu_rv64-2.C}    | 134 ++---
 .../{vadd_vv_tumu-3.C => vadd_vx_tumu_rv64-3.C}    | 134 ++---
 .../base/{vand_vv_mu-1.C => vand_vx_mu_rv32-1.C}   | 129 +++--
 .../base/{vand_vv_mu-2.C => vand_vx_mu_rv32-2.C}   | 129 +++--
 .../base/{vand_vv_mu-3.C => vand_vx_mu_rv32-3.C}   | 129 +++--
 .../base/{vand_vv_mu-1.C => vand_vx_mu_rv64-1.C}   | 134 ++---
 .../base/{vand_vv_mu-2.C => vand_vx_mu_rv64-2.C}   | 134 ++---
 .../base/{vand_vv_mu-3.C => vand_vx_mu_rv64-3.C}   | 134 ++---
 .../g++.target/riscv/rvv/base/vand_vx_rv32-1.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vand_vx_rv32-2.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vand_vx_rv32-3.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vand_vx_rv64-1.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vand_vx_rv64-2.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vand_vx_rv64-3.C     | 578 +++++++++++++++++++++
 .../base/{vand_vv_tu-1.C => vand_vx_tu_rv32-1.C}   | 129 +++--
 .../base/{vand_vv_tu-2.C => vand_vx_tu_rv32-2.C}   | 129 +++--
 .../base/{vand_vv_tu-3.C => vand_vx_tu_rv32-3.C}   | 129 +++--
 .../base/{vand_vv_tu-1.C => vand_vx_tu_rv64-1.C}   | 134 ++---
 .../base/{vand_vv_tu-2.C => vand_vx_tu_rv64-2.C}   | 134 ++---
 .../base/{vand_vv_tu-3.C => vand_vx_tu_rv64-3.C}   | 134 ++---
 .../base/{vand_vv_tum-1.C => vand_vx_tum_rv32-1.C} | 129 +++--
 .../base/{vand_vv_tum-2.C => vand_vx_tum_rv32-2.C} | 129 +++--
 .../base/{vand_vv_tum-3.C => vand_vx_tum_rv32-3.C} | 129 +++--
 .../base/{vand_vv_tum-1.C => vand_vx_tum_rv64-1.C} | 134 ++---
 .../base/{vand_vv_tum-2.C => vand_vx_tum_rv64-2.C} | 134 ++---
 .../base/{vand_vv_tum-3.C => vand_vx_tum_rv64-3.C} | 134 ++---
 .../{vand_vv_tumu-1.C => vand_vx_tumu_rv32-1.C}    | 129 +++--
 .../{vand_vv_tumu-2.C => vand_vx_tumu_rv32-2.C}    | 129 +++--
 .../{vand_vv_tumu-3.C => vand_vx_tumu_rv32-3.C}    | 129 +++--
 .../{vand_vv_tumu-1.C => vand_vx_tumu_rv64-1.C}    | 134 ++---
 .../{vand_vv_tumu-2.C => vand_vx_tumu_rv64-2.C}    | 134 ++---
 .../{vand_vv_tumu-3.C => vand_vx_tumu_rv64-3.C}    | 134 ++---
 .../base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv32-1.C}   |  85 ++-
 .../base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv32-2.C}   |  85 ++-
 .../base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv32-3.C}   |  85 ++-
 .../base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv64-1.C}   |  90 ++--
 .../base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv64-2.C}   |  90 ++--
 .../base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv64-3.C}   |  90 ++--
 .../g++.target/riscv/rvv/base/vdiv_vx_rv32-1.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vdiv_vx_rv32-2.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vdiv_vx_rv32-3.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vdiv_vx_rv64-1.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vdiv_vx_rv64-2.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vdiv_vx_rv64-3.C     | 314 +++++++++++
 .../base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv32-1.C}   |  85 ++-
 .../base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv32-2.C}   |  85 ++-
 .../base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv32-3.C}   |  85 ++-
 .../base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv64-1.C}   |  90 ++--
 .../base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv64-2.C}   |  90 ++--
 .../base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv64-3.C}   |  90 ++--
 .../base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv32-1.C} |  85 ++-
 .../base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv32-2.C} |  85 ++-
 .../base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv32-3.C} |  85 ++-
 .../base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv64-1.C} |  90 ++--
 .../base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv64-2.C} |  90 ++--
 .../base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv64-3.C} |  90 ++--
 .../{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv32-1.C}    |  85 ++-
 .../{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv32-2.C}    |  85 ++-
 .../{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv32-3.C}    |  85 ++-
 .../{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv64-1.C}    |  90 ++--
 .../{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv64-2.C}    |  90 ++--
 .../{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv64-3.C}    |  90 ++--
 .../base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv32-1.C} |  85 ++-
 .../base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv32-2.C} |  85 ++-
 .../base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv32-3.C} |  85 ++-
 .../base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv64-1.C} |  90 ++--
 .../base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv64-2.C} |  90 ++--
 .../base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv64-3.C} |  90 ++--
 .../g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C    | 314 +++++++++++
 .../base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv32-1.C} |  85 ++-
 .../base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv32-2.C} |  85 ++-
 .../base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv32-3.C} |  85 ++-
 .../base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv64-1.C} |  90 ++--
 .../base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv64-2.C} |  90 ++--
 .../base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv64-3.C} |  90 ++--
 .../{vdivu_vv_tum-1.C => vdivu_vx_tum_rv32-1.C}    |  85 ++-
 .../{vdivu_vv_tum-2.C => vdivu_vx_tum_rv32-2.C}    |  85 ++-
 .../{vdivu_vv_tum-3.C => vdivu_vx_tum_rv32-3.C}    |  85 ++-
 .../{vdivu_vv_tum-1.C => vdivu_vx_tum_rv64-1.C}    |  90 ++--
 .../{vdivu_vv_tum-2.C => vdivu_vx_tum_rv64-2.C}    |  90 ++--
 .../{vdivu_vv_tum-3.C => vdivu_vx_tum_rv64-3.C}    |  90 ++--
 .../{vdivu_vv_tumu-1.C => vdivu_vx_tumu_rv32-1.C}  |  85 ++-
 .../{vdivu_vv_tumu-2.C => vdivu_vx_tumu_rv32-2.C}  |  85 ++-
 .../{vdivu_vv_tumu-3.C => vdivu_vx_tumu_rv32-3.C}  |  85 ++-
 .../{vdivu_vv_tumu-1.C => vdivu_vx_tumu_rv64-1.C}  |  90 ++--
 .../{vdivu_vv_tumu-2.C => vdivu_vx_tumu_rv64-2.C}  |  90 ++--
 .../{vdivu_vv_tumu-3.C => vdivu_vx_tumu_rv64-3.C}  |  90 ++--
 .../base/{vmax_vv_mu-1.C => vmax_vx_mu_rv32-1.C}   |  85 ++-
 .../base/{vmax_vv_mu-2.C => vmax_vx_mu_rv32-2.C}   |  85 ++-
 .../base/{vmax_vv_mu-3.C => vmax_vx_mu_rv32-3.C}   |  85 ++-
 .../base/{vmax_vv_mu-1.C => vmax_vx_mu_rv64-1.C}   |  90 ++--
 .../base/{vmax_vv_mu-2.C => vmax_vx_mu_rv64-2.C}   |  90 ++--
 .../base/{vmax_vv_mu-3.C => vmax_vx_mu_rv64-3.C}   |  90 ++--
 .../g++.target/riscv/rvv/base/vmax_vx_rv32-1.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmax_vx_rv32-2.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmax_vx_rv32-3.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmax_vx_rv64-1.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vmax_vx_rv64-2.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vmax_vx_rv64-3.C     | 314 +++++++++++
 .../base/{vmax_vv_tu-1.C => vmax_vx_tu_rv32-1.C}   |  85 ++-
 .../base/{vmax_vv_tu-2.C => vmax_vx_tu_rv32-2.C}   |  85 ++-
 .../base/{vmax_vv_tu-3.C => vmax_vx_tu_rv32-3.C}   |  85 ++-
 .../base/{vmax_vv_tu-1.C => vmax_vx_tu_rv64-1.C}   |  90 ++--
 .../base/{vmax_vv_tu-2.C => vmax_vx_tu_rv64-2.C}   |  90 ++--
 .../base/{vmax_vv_tu-3.C => vmax_vx_tu_rv64-3.C}   |  90 ++--
 .../base/{vmax_vv_tum-1.C => vmax_vx_tum_rv32-1.C} |  85 ++-
 .../base/{vmax_vv_tum-2.C => vmax_vx_tum_rv32-2.C} |  85 ++-
 .../base/{vmax_vv_tum-3.C => vmax_vx_tum_rv32-3.C} |  85 ++-
 .../base/{vmax_vv_tum-1.C => vmax_vx_tum_rv64-1.C} |  90 ++--
 .../base/{vmax_vv_tum-2.C => vmax_vx_tum_rv64-2.C} |  90 ++--
 .../base/{vmax_vv_tum-3.C => vmax_vx_tum_rv64-3.C} |  90 ++--
 .../{vmax_vv_tumu-1.C => vmax_vx_tumu_rv32-1.C}    |  85 ++-
 .../{vmax_vv_tumu-2.C => vmax_vx_tumu_rv32-2.C}    |  85 ++-
 .../{vmax_vv_tumu-3.C => vmax_vx_tumu_rv32-3.C}    |  85 ++-
 .../{vmax_vv_tumu-1.C => vmax_vx_tumu_rv64-1.C}    |  90 ++--
 .../{vmax_vv_tumu-2.C => vmax_vx_tumu_rv64-2.C}    |  90 ++--
 .../{vmax_vv_tumu-3.C => vmax_vx_tumu_rv64-3.C}    |  90 ++--
 .../base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv32-1.C} |  85 ++-
 .../base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv32-2.C} |  85 ++-
 .../base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv32-3.C} |  85 ++-
 .../base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv64-1.C} |  90 ++--
 .../base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv64-2.C} |  90 ++--
 .../base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv64-3.C} |  90 ++--
 .../g++.target/riscv/rvv/base/vmaxu_vx_rv32-1.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vx_rv32-2.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vx_rv32-3.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vx_rv64-1.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vx_rv64-2.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vmaxu_vx_rv64-3.C    | 314 +++++++++++
 .../base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv32-1.C} |  85 ++-
 .../base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv32-2.C} |  85 ++-
 .../base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv32-3.C} |  85 ++-
 .../base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv64-1.C} |  90 ++--
 .../base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv64-2.C} |  90 ++--
 .../base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv64-3.C} |  90 ++--
 .../{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv32-1.C}    |  85 ++-
 .../{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv32-2.C}    |  85 ++-
 .../{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv32-3.C}    |  85 ++-
 .../{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv64-1.C}    |  90 ++--
 .../{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv64-2.C}    |  90 ++--
 .../{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv64-3.C}    |  90 ++--
 .../{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_rv32-1.C}  |  85 ++-
 .../{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_rv32-2.C}  |  85 ++-
 .../{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_rv32-3.C}  |  85 ++-
 .../{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_rv64-1.C}  |  90 ++--
 .../{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_rv64-2.C}  |  90 ++--
 .../{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_rv64-3.C}  |  90 ++--
 .../base/{vmin_vv_mu-1.C => vmin_vx_mu_rv32-1.C}   |  85 ++-
 .../base/{vmin_vv_mu-2.C => vmin_vx_mu_rv32-2.C}   |  85 ++-
 .../base/{vmin_vv_mu-3.C => vmin_vx_mu_rv32-3.C}   |  85 ++-
 .../base/{vmin_vv_mu-1.C => vmin_vx_mu_rv64-1.C}   |  90 ++--
 .../base/{vmin_vv_mu-2.C => vmin_vx_mu_rv64-2.C}   |  90 ++--
 .../base/{vmin_vv_mu-3.C => vmin_vx_mu_rv64-3.C}   |  90 ++--
 .../g++.target/riscv/rvv/base/vmin_vx_rv32-1.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmin_vx_rv32-2.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmin_vx_rv32-3.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vmin_vx_rv64-1.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vmin_vx_rv64-2.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vmin_vx_rv64-3.C     | 314 +++++++++++
 .../base/{vmin_vv_tu-1.C => vmin_vx_tu_rv32-1.C}   |  85 ++-
 .../base/{vmin_vv_tu-2.C => vmin_vx_tu_rv32-2.C}   |  85 ++-
 .../base/{vmin_vv_tu-3.C => vmin_vx_tu_rv32-3.C}   |  85 ++-
 .../base/{vmin_vv_tu-1.C => vmin_vx_tu_rv64-1.C}   |  90 ++--
 .../base/{vmin_vv_tu-2.C => vmin_vx_tu_rv64-2.C}   |  90 ++--
 .../base/{vmin_vv_tu-3.C => vmin_vx_tu_rv64-3.C}   |  90 ++--
 .../base/{vmin_vv_tum-1.C => vmin_vx_tum_rv32-1.C} |  85 ++-
 .../base/{vmin_vv_tum-2.C => vmin_vx_tum_rv32-2.C} |  85 ++-
 .../base/{vmin_vv_tum-3.C => vmin_vx_tum_rv32-3.C} |  85 ++-
 .../base/{vmin_vv_tum-1.C => vmin_vx_tum_rv64-1.C} |  90 ++--
 .../base/{vmin_vv_tum-2.C => vmin_vx_tum_rv64-2.C} |  90 ++--
 .../base/{vmin_vv_tum-3.C => vmin_vx_tum_rv64-3.C} |  90 ++--
 .../{vmin_vv_tumu-1.C => vmin_vx_tumu_rv32-1.C}    |  85 ++-
 .../{vmin_vv_tumu-2.C => vmin_vx_tumu_rv32-2.C}    |  85 ++-
 .../{vmin_vv_tumu-3.C => vmin_vx_tumu_rv32-3.C}    |  85 ++-
 .../{vmin_vv_tumu-1.C => vmin_vx_tumu_rv64-1.C}    |  90 ++--
 .../{vmin_vv_tumu-2.C => vmin_vx_tumu_rv64-2.C}    |  90 ++--
 .../{vmin_vv_tumu-3.C => vmin_vx_tumu_rv64-3.C}    |  90 ++--
 .../base/{vminu_vv_mu-1.C => vminu_vx_mu_rv32-1.C} |  85 ++-
 .../base/{vminu_vv_mu-2.C => vminu_vx_mu_rv32-2.C} |  85 ++-
 .../base/{vminu_vv_mu-3.C => vminu_vx_mu_rv32-3.C} |  85 ++-
 .../base/{vminu_vv_mu-1.C => vminu_vx_mu_rv64-1.C} |  90 ++--
 .../base/{vminu_vv_mu-2.C => vminu_vx_mu_rv64-2.C} |  90 ++--
 .../base/{vminu_vv_mu-3.C => vminu_vx_mu_rv64-3.C} |  90 ++--
 .../g++.target/riscv/rvv/base/vminu_vx_rv32-1.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vminu_vx_rv32-2.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vminu_vx_rv32-3.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vminu_vx_rv64-1.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vminu_vx_rv64-2.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vminu_vx_rv64-3.C    | 314 +++++++++++
 .../base/{vminu_vv_tu-1.C => vminu_vx_tu_rv32-1.C} |  85 ++-
 .../base/{vminu_vv_tu-2.C => vminu_vx_tu_rv32-2.C} |  85 ++-
 .../base/{vminu_vv_tu-3.C => vminu_vx_tu_rv32-3.C} |  85 ++-
 .../base/{vminu_vv_tu-1.C => vminu_vx_tu_rv64-1.C} |  90 ++--
 .../base/{vminu_vv_tu-2.C => vminu_vx_tu_rv64-2.C} |  90 ++--
 .../base/{vminu_vv_tu-3.C => vminu_vx_tu_rv64-3.C} |  90 ++--
 .../{vminu_vv_tum-1.C => vminu_vx_tum_rv32-1.C}    |  85 ++-
 .../{vminu_vv_tum-2.C => vminu_vx_tum_rv32-2.C}    |  85 ++-
 .../{vminu_vv_tum-3.C => vminu_vx_tum_rv32-3.C}    |  85 ++-
 .../{vminu_vv_tum-1.C => vminu_vx_tum_rv64-1.C}    |  90 ++--
 .../{vminu_vv_tum-2.C => vminu_vx_tum_rv64-2.C}    |  90 ++--
 .../{vminu_vv_tum-3.C => vminu_vx_tum_rv64-3.C}    |  90 ++--
 .../{vminu_vv_tumu-1.C => vminu_vx_tumu_rv32-1.C}  |  85 ++-
 .../{vminu_vv_tumu-2.C => vminu_vx_tumu_rv32-2.C}  |  85 ++-
 .../{vminu_vv_tumu-3.C => vminu_vx_tumu_rv32-3.C}  |  85 ++-
 .../{vminu_vv_tumu-1.C => vminu_vx_tumu_rv64-1.C}  |  90 ++--
 .../{vminu_vv_tumu-2.C => vminu_vx_tumu_rv64-2.C}  |  90 ++--
 .../{vminu_vv_tumu-3.C => vminu_vx_tumu_rv64-3.C}  |  90 ++--
 .../g++.target/riscv/rvv/base/vmul_vv-1.C          | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv-2.C          | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv-3.C          | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_mu-1.C       | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_mu-2.C       | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_mu-3.C       | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tu-1.C       | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tu-2.C       | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tu-3.C       | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tum-1.C      | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tum-2.C      | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tum-3.C      | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tumu-1.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tumu-2.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vv_tumu-3.C     | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-1.C  | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-2.C  | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-3.C  | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-1.C  | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-2.C  | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-3.C  | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_rv32-1.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_rv32-2.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_rv32-3.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_rv64-1.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_rv64-2.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_rv64-3.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-1.C  | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-2.C  | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-3.C  | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-1.C  | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-2.C  | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-3.C  | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-1.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-2.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-3.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-1.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-2.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-3.C | 292 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv32-1.C           | 289 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv32-2.C           | 289 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv32-3.C           | 289 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv64-1.C           | 292 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv64-2.C           | 292 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv64-3.C           | 292 +++++++++++
 .../rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv32-1.C} | 129 +++--
 .../rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv32-2.C} | 129 +++--
 .../rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv32-3.C} | 129 +++--
 .../rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv64-1.C} | 134 ++---
 .../rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv64-2.C} | 134 ++---
 .../rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv64-3.C} | 134 ++---
 .../g++.target/riscv/rvv/base/vor_vx_rv32-1.C      | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vor_vx_rv32-2.C      | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vor_vx_rv32-3.C      | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vor_vx_rv64-1.C      | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vor_vx_rv64-2.C      | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vor_vx_rv64-3.C      | 578 +++++++++++++++++++++
 .../rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv32-1.C} | 129 +++--
 .../rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv32-2.C} | 129 +++--
 .../rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv32-3.C} | 129 +++--
 .../rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv64-1.C} | 134 ++---
 .../rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv64-2.C} | 134 ++---
 .../rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv64-3.C} | 134 ++---
 .../base/{vor_vv_tum-1.C => vor_vx_tum_rv32-1.C}   | 129 +++--
 .../base/{vor_vv_tum-2.C => vor_vx_tum_rv32-2.C}   | 129 +++--
 .../base/{vor_vv_tum-3.C => vor_vx_tum_rv32-3.C}   | 129 +++--
 .../base/{vor_vv_tum-1.C => vor_vx_tum_rv64-1.C}   | 134 ++---
 .../base/{vor_vv_tum-2.C => vor_vx_tum_rv64-2.C}   | 134 ++---
 .../base/{vor_vv_tum-3.C => vor_vx_tum_rv64-3.C}   | 134 ++---
 .../base/{vor_vv_tumu-1.C => vor_vx_tumu_rv32-1.C} | 129 +++--
 .../base/{vor_vv_tumu-2.C => vor_vx_tumu_rv32-2.C} | 129 +++--
 .../base/{vor_vv_tumu-3.C => vor_vx_tumu_rv32-3.C} | 129 +++--
 .../base/{vor_vv_tumu-1.C => vor_vx_tumu_rv64-1.C} | 134 ++---
 .../base/{vor_vv_tumu-2.C => vor_vx_tumu_rv64-2.C} | 134 ++---
 .../base/{vor_vv_tumu-3.C => vor_vx_tumu_rv64-3.C} | 134 ++---
 .../base/{vrem_vv_mu-1.C => vrem_vx_mu_rv32-1.C}   |  85 ++-
 .../base/{vrem_vv_mu-2.C => vrem_vx_mu_rv32-2.C}   |  85 ++-
 .../base/{vrem_vv_mu-3.C => vrem_vx_mu_rv32-3.C}   |  85 ++-
 .../base/{vrem_vv_mu-1.C => vrem_vx_mu_rv64-1.C}   |  90 ++--
 .../base/{vrem_vv_mu-2.C => vrem_vx_mu_rv64-2.C}   |  90 ++--
 .../base/{vrem_vv_mu-3.C => vrem_vx_mu_rv64-3.C}   |  90 ++--
 .../g++.target/riscv/rvv/base/vrem_vx_rv32-1.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vrem_vx_rv32-2.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vrem_vx_rv32-3.C     | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vrem_vx_rv64-1.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vrem_vx_rv64-2.C     | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vrem_vx_rv64-3.C     | 314 +++++++++++
 .../base/{vrem_vv_tu-1.C => vrem_vx_tu_rv32-1.C}   |  85 ++-
 .../base/{vrem_vv_tu-2.C => vrem_vx_tu_rv32-2.C}   |  85 ++-
 .../base/{vrem_vv_tu-3.C => vrem_vx_tu_rv32-3.C}   |  85 ++-
 .../base/{vrem_vv_tu-1.C => vrem_vx_tu_rv64-1.C}   |  90 ++--
 .../base/{vrem_vv_tu-2.C => vrem_vx_tu_rv64-2.C}   |  90 ++--
 .../base/{vrem_vv_tu-3.C => vrem_vx_tu_rv64-3.C}   |  90 ++--
 .../base/{vrem_vv_tum-1.C => vrem_vx_tum_rv32-1.C} |  85 ++-
 .../base/{vrem_vv_tum-2.C => vrem_vx_tum_rv32-2.C} |  85 ++-
 .../base/{vrem_vv_tum-3.C => vrem_vx_tum_rv32-3.C} |  85 ++-
 .../base/{vrem_vv_tum-1.C => vrem_vx_tum_rv64-1.C} |  90 ++--
 .../base/{vrem_vv_tum-2.C => vrem_vx_tum_rv64-2.C} |  90 ++--
 .../base/{vrem_vv_tum-3.C => vrem_vx_tum_rv64-3.C} |  90 ++--
 .../{vrem_vv_tumu-1.C => vrem_vx_tumu_rv32-1.C}    |  85 ++-
 .../{vrem_vv_tumu-2.C => vrem_vx_tumu_rv32-2.C}    |  85 ++-
 .../{vrem_vv_tumu-3.C => vrem_vx_tumu_rv32-3.C}    |  85 ++-
 .../{vrem_vv_tumu-1.C => vrem_vx_tumu_rv64-1.C}    |  90 ++--
 .../{vrem_vv_tumu-2.C => vrem_vx_tumu_rv64-2.C}    |  90 ++--
 .../{vrem_vv_tumu-3.C => vrem_vx_tumu_rv64-3.C}    |  90 ++--
 .../base/{vremu_vv_mu-1.C => vremu_vx_mu_rv32-1.C} |  85 ++-
 .../base/{vremu_vv_mu-2.C => vremu_vx_mu_rv32-2.C} |  85 ++-
 .../base/{vremu_vv_mu-3.C => vremu_vx_mu_rv32-3.C} |  85 ++-
 .../base/{vremu_vv_mu-1.C => vremu_vx_mu_rv64-1.C} |  90 ++--
 .../base/{vremu_vv_mu-2.C => vremu_vx_mu_rv64-2.C} |  90 ++--
 .../base/{vremu_vv_mu-3.C => vremu_vx_mu_rv64-3.C} |  90 ++--
 .../g++.target/riscv/rvv/base/vremu_vx_rv32-1.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vremu_vx_rv32-2.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vremu_vx_rv32-3.C    | 308 +++++++++++
 .../g++.target/riscv/rvv/base/vremu_vx_rv64-1.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vremu_vx_rv64-2.C    | 314 +++++++++++
 .../g++.target/riscv/rvv/base/vremu_vx_rv64-3.C    | 314 +++++++++++
 .../base/{vremu_vv_tu-1.C => vremu_vx_tu_rv32-1.C} |  85 ++-
 .../base/{vremu_vv_tu-2.C => vremu_vx_tu_rv32-2.C} |  85 ++-
 .../base/{vremu_vv_tu-3.C => vremu_vx_tu_rv32-3.C} |  85 ++-
 .../base/{vremu_vv_tu-1.C => vremu_vx_tu_rv64-1.C} |  90 ++--
 .../base/{vremu_vv_tu-2.C => vremu_vx_tu_rv64-2.C} |  90 ++--
 .../base/{vremu_vv_tu-3.C => vremu_vx_tu_rv64-3.C} |  90 ++--
 .../{vremu_vv_tum-1.C => vremu_vx_tum_rv32-1.C}    |  85 ++-
 .../{vremu_vv_tum-2.C => vremu_vx_tum_rv32-2.C}    |  85 ++-
 .../{vremu_vv_tum-3.C => vremu_vx_tum_rv32-3.C}    |  85 ++-
 .../{vremu_vv_tum-1.C => vremu_vx_tum_rv64-1.C}    |  90 ++--
 .../{vremu_vv_tum-2.C => vremu_vx_tum_rv64-2.C}    |  90 ++--
 .../{vremu_vv_tum-3.C => vremu_vx_tum_rv64-3.C}    |  90 ++--
 .../{vremu_vv_tumu-1.C => vremu_vx_tumu_rv32-1.C}  |  85 ++-
 .../{vremu_vv_tumu-2.C => vremu_vx_tumu_rv32-2.C}  |  85 ++-
 .../{vremu_vv_tumu-3.C => vremu_vx_tumu_rv32-3.C}  |  85 ++-
 .../{vremu_vv_tumu-1.C => vremu_vx_tumu_rv64-1.C}  |  90 ++--
 .../{vremu_vv_tumu-2.C => vremu_vx_tumu_rv64-2.C}  |  90 ++--
 .../{vremu_vv_tumu-3.C => vremu_vx_tumu_rv64-3.C}  |  90 ++--
 .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C    | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C    | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C    | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C    | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C    | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C    | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C | 289 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C | 292 +++++++++++
 .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-1.C           | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-2.C           | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-3.C           | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-1.C           | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-2.C           | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-3.C           | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-1.C          | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-2.C          | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-3.C          | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-1.C          | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-2.C          | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-3.C          | 292 +++++++++++
 .../base/{vsub_vv_mu-1.C => vsub_vx_mu_rv32-1.C}   | 129 +++--
 .../base/{vsub_vv_mu-2.C => vsub_vx_mu_rv32-2.C}   | 129 +++--
 .../base/{vsub_vv_mu-3.C => vsub_vx_mu_rv32-3.C}   | 129 +++--
 .../base/{vsub_vv_mu-1.C => vsub_vx_mu_rv64-1.C}   | 134 ++---
 .../base/{vsub_vv_mu-2.C => vsub_vx_mu_rv64-2.C}   | 134 ++---
 .../base/{vsub_vv_mu-3.C => vsub_vx_mu_rv64-3.C}   | 134 ++---
 .../g++.target/riscv/rvv/base/vsub_vx_rv32-1.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsub_vx_rv32-2.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsub_vx_rv32-3.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsub_vx_rv64-1.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsub_vx_rv64-2.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vsub_vx_rv64-3.C     | 578 +++++++++++++++++++++
 .../base/{vsub_vv_tu-1.C => vsub_vx_tu_rv32-1.C}   | 129 +++--
 .../base/{vsub_vv_tu-2.C => vsub_vx_tu_rv32-2.C}   | 129 +++--
 .../base/{vsub_vv_tu-3.C => vsub_vx_tu_rv32-3.C}   | 129 +++--
 .../base/{vsub_vv_tu-1.C => vsub_vx_tu_rv64-1.C}   | 134 ++---
 .../base/{vsub_vv_tu-2.C => vsub_vx_tu_rv64-2.C}   | 134 ++---
 .../base/{vsub_vv_tu-3.C => vsub_vx_tu_rv64-3.C}   | 134 ++---
 .../base/{vsub_vv_tum-1.C => vsub_vx_tum_rv32-1.C} | 129 +++--
 .../base/{vsub_vv_tum-2.C => vsub_vx_tum_rv32-2.C} | 129 +++--
 .../base/{vsub_vv_tum-3.C => vsub_vx_tum_rv32-3.C} | 129 +++--
 .../base/{vsub_vv_tum-1.C => vsub_vx_tum_rv64-1.C} | 134 ++---
 .../base/{vsub_vv_tum-2.C => vsub_vx_tum_rv64-2.C} | 134 ++---
 .../base/{vsub_vv_tum-3.C => vsub_vx_tum_rv64-3.C} | 134 ++---
 .../{vsub_vv_tumu-1.C => vsub_vx_tumu_rv32-1.C}    | 129 +++--
 .../{vsub_vv_tumu-2.C => vsub_vx_tumu_rv32-2.C}    | 129 +++--
 .../{vsub_vv_tumu-3.C => vsub_vx_tumu_rv32-3.C}    | 129 +++--
 .../{vsub_vv_tumu-1.C => vsub_vx_tumu_rv64-1.C}    | 134 ++---
 .../{vsub_vv_tumu-2.C => vsub_vx_tumu_rv64-2.C}    | 134 ++---
 .../{vsub_vv_tumu-3.C => vsub_vx_tumu_rv64-3.C}    | 134 ++---
 .../base/{vxor_vv_mu-1.C => vxor_vx_mu_rv32-1.C}   | 129 +++--
 .../base/{vxor_vv_mu-2.C => vxor_vx_mu_rv32-2.C}   | 129 +++--
 .../base/{vxor_vv_mu-3.C => vxor_vx_mu_rv32-3.C}   | 129 +++--
 .../base/{vxor_vv_mu-1.C => vxor_vx_mu_rv64-1.C}   | 134 ++---
 .../base/{vxor_vv_mu-2.C => vxor_vx_mu_rv64-2.C}   | 134 ++---
 .../base/{vxor_vv_mu-3.C => vxor_vx_mu_rv64-3.C}   | 134 ++---
 .../g++.target/riscv/rvv/base/vxor_vx_rv32-1.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vxor_vx_rv32-2.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vxor_vx_rv32-3.C     | 572 ++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vxor_vx_rv64-1.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vxor_vx_rv64-2.C     | 578 +++++++++++++++++++++
 .../g++.target/riscv/rvv/base/vxor_vx_rv64-3.C     | 578 +++++++++++++++++++++
 .../base/{vxor_vv_tu-1.C => vxor_vx_tu_rv32-1.C}   | 129 +++--
 .../base/{vxor_vv_tu-2.C => vxor_vx_tu_rv32-2.C}   | 129 +++--
 .../base/{vxor_vv_tu-3.C => vxor_vx_tu_rv32-3.C}   | 129 +++--
 .../base/{vxor_vv_tu-1.C => vxor_vx_tu_rv64-1.C}   | 134 ++---
 .../base/{vxor_vv_tu-2.C => vxor_vx_tu_rv64-2.C}   | 134 ++---
 .../base/{vxor_vv_tu-3.C => vxor_vx_tu_rv64-3.C}   | 134 ++---
 .../base/{vxor_vv_tum-1.C => vxor_vx_tum_rv32-1.C} | 129 +++--
 .../base/{vxor_vv_tum-2.C => vxor_vx_tum_rv32-2.C} | 129 +++--
 .../base/{vxor_vv_tum-3.C => vxor_vx_tum_rv32-3.C} | 129 +++--
 .../base/{vxor_vv_tum-1.C => vxor_vx_tum_rv64-1.C} | 134 ++---
 .../base/{vxor_vv_tum-2.C => vxor_vx_tum_rv64-2.C} | 134 ++---
 .../base/{vxor_vv_tum-3.C => vxor_vx_tum_rv64-3.C} | 134 ++---
 .../{vxor_vv_tumu-1.C => vxor_vx_tumu_rv32-1.C}    | 129 +++--
 .../{vxor_vv_tumu-2.C => vxor_vx_tumu_rv32-2.C}    | 129 +++--
 .../{vxor_vv_tumu-3.C => vxor_vx_tumu_rv32-3.C}    | 129 +++--
 .../{vxor_vv_tumu-1.C => vxor_vx_tumu_rv64-1.C}    | 134 ++---
 .../{vxor_vv_tumu-2.C => vxor_vx_tumu_rv64-2.C}    | 134 ++---
 .../{vxor_vv_tumu-3.C => vxor_vx_tumu_rv64-3.C}    | 134 ++---
 gcc/testsuite/gcc.target/i386/pr108724.c           |  15 +
 ...t_vx_constraint-1.c => binop_vx_constraint-1.c} |  62 ++-
 ..._vv_constraint-1.c => binop_vx_constraint-10.c} |  60 +--
 ..._vv_constraint-1.c => binop_vx_constraint-11.c} |  60 +--
 ..._vv_constraint-1.c => binop_vx_constraint-12.c} |  88 ++--
 ..._vv_constraint-1.c => binop_vx_constraint-13.c} |  60 +--
 ..._vv_constraint-1.c => binop_vx_constraint-14.c} |  60 +--
 ..._vx_constraint-1.c => binop_vx_constraint-15.c} |  62 ++-
 ..._vx_constraint-1.c => binop_vx_constraint-16.c} |  90 ++--
 ..._vx_constraint-1.c => binop_vx_constraint-17.c} |  90 ++--
 ..._vx_constraint-1.c => binop_vx_constraint-18.c} |  62 ++-
 ..._vx_constraint-1.c => binop_vx_constraint-19.c} |  90 ++--
 ...t_vx_constraint-1.c => binop_vx_constraint-2.c} |  62 ++-
 ..._vx_constraint-1.c => binop_vx_constraint-20.c} |  62 ++-
 ..._vx_constraint-1.c => binop_vx_constraint-21.c} |  90 ++--
 ..._vx_constraint-1.c => binop_vx_constraint-22.c} |  62 ++-
 .../riscv/rvv/base/binop_vx_constraint-23.c        | 160 ++++++
 .../riscv/rvv/base/binop_vx_constraint-24.c        | 132 +++++
 .../riscv/rvv/base/binop_vx_constraint-25.c        | 160 ++++++
 .../riscv/rvv/base/binop_vx_constraint-26.c        | 132 +++++
 ..._vx_constraint-1.c => binop_vx_constraint-27.c} |  90 ++--
 ..._vx_constraint-1.c => binop_vx_constraint-28.c} |  62 ++-
 .../riscv/rvv/base/binop_vx_constraint-29.c        | 160 ++++++
 ...p_vv_constraint-1.c => binop_vx_constraint-3.c} |  60 +--
 .../riscv/rvv/base/binop_vx_constraint-30.c        | 132 +++++
 .../riscv/rvv/base/binop_vx_constraint-31.c        | 160 ++++++
 .../riscv/rvv/base/binop_vx_constraint-32.c        | 132 +++++
 .../riscv/rvv/base/binop_vx_constraint-33.c        | 160 ++++++
 .../riscv/rvv/base/binop_vx_constraint-34.c        | 132 +++++
 .../riscv/rvv/base/binop_vx_constraint-35.c        | 160 ++++++
 .../riscv/rvv/base/binop_vx_constraint-36.c        | 132 +++++
 ..._vx_constraint-1.c => binop_vx_constraint-37.c} |  62 ++-
 ..._vx_constraint-1.c => binop_vx_constraint-38.c} |  62 ++-
 ..._vv_constraint-1.c => binop_vx_constraint-39.c} |  60 +--
 ...p_vv_constraint-1.c => binop_vx_constraint-4.c} |  88 ++--
 ..._vv_constraint-1.c => binop_vx_constraint-40.c} |  88 ++--
 ..._vv_constraint-1.c => binop_vx_constraint-41.c} |  60 +--
 ..._vx_constraint-1.c => binop_vx_constraint-42.c} |  62 ++-
 ..._vx_constraint-1.c => binop_vx_constraint-43.c} |  62 ++-
 ..._vv_constraint-1.c => binop_vx_constraint-44.c} |  88 ++--
 .../riscv/rvv/base/binop_vx_constraint-45.c        | 123 +++++
 .../riscv/rvv/base/binop_vx_constraint-46.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-47.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-48.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-49.c        |  16 +
 ...t_vx_constraint-1.c => binop_vx_constraint-5.c} |  62 ++-
 .../riscv/rvv/base/binop_vx_constraint-50.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-51.c        | 123 +++++
 .../riscv/rvv/base/binop_vx_constraint-52.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-53.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-54.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-55.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-56.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-57.c        | 123 +++++
 .../riscv/rvv/base/binop_vx_constraint-58.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-59.c        |  16 +
 ...t_vx_constraint-1.c => binop_vx_constraint-6.c} |  62 ++-
 .../riscv/rvv/base/binop_vx_constraint-60.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-61.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-62.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-63.c        | 123 +++++
 .../riscv/rvv/base/binop_vx_constraint-64.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-65.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-66.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-67.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-68.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-69.c        | 123 +++++
 ...p_vv_constraint-1.c => binop_vx_constraint-7.c} |  60 +--
 .../riscv/rvv/base/binop_vx_constraint-70.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-71.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-72.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-73.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-74.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-75.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-76.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-77.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-78.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-79.c        |  18 +
 ...p_vv_constraint-1.c => binop_vx_constraint-8.c} |  88 ++--
 .../riscv/rvv/base/binop_vx_constraint-80.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-81.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-82.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-83.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-84.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-85.c        | 123 +++++
 .../riscv/rvv/base/binop_vx_constraint-86.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-87.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-88.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-89.c        |  16 +
 ...t_vx_constraint-1.c => binop_vx_constraint-9.c} |  62 ++-
 .../riscv/rvv/base/binop_vx_constraint-90.c        |  18 +
 .../riscv/rvv/base/binop_vx_constraint-91.c        | 123 +++++
 .../riscv/rvv/base/binop_vx_constraint-92.c        |  72 +++
 .../riscv/rvv/base/binop_vx_constraint-93.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-94.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-95.c        |  16 +
 .../riscv/rvv/base/binop_vx_constraint-96.c        |  18 +
 .../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_rv32-1.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_rv32-2.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_rv32-3.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_rv64-1.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_rv64-2.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_rv64-3.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-3.c | 292 +++++++++++
 .../riscv/rvv/base/vadd_vx_tumu_rv32-1.c           | 289 +++++++++++
 .../riscv/rvv/base/vadd_vx_tumu_rv32-2.c           | 289 +++++++++++
 .../riscv/rvv/base/vadd_vx_tumu_rv32-3.c           | 289 +++++++++++
 .../riscv/rvv/base/vadd_vx_tumu_rv64-1.c           | 292 +++++++++++
 .../riscv/rvv/base/vadd_vx_tumu_rv64-2.c           | 292 +++++++++++
 .../riscv/rvv/base/vadd_vx_tumu_rv64-3.c           | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_m_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_m_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_m_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_m_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_m_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_m_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_rv32-1.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_rv32-2.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_rv32-3.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_rv64-1.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_rv64-2.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_rv64-3.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-3.c | 292 +++++++++++
 .../riscv/rvv/base/vand_vx_tumu_rv32-1.c           | 289 +++++++++++
 .../riscv/rvv/base/vand_vx_tumu_rv32-2.c           | 289 +++++++++++
 .../riscv/rvv/base/vand_vx_tumu_rv32-3.c           | 289 +++++++++++
 .../riscv/rvv/base/vand_vx_tumu_rv64-1.c           | 292 +++++++++++
 .../riscv/rvv/base/vand_vx_tumu_rv64-2.c           | 292 +++++++++++
 .../riscv/rvv/base/vand_vx_tumu_rv64-3.c           | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-1.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-2.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-3.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-1.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-2.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-3.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_rv32-1.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_rv32-2.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_rv32-3.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_rv64-1.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_rv64-2.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_rv64-3.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vdiv_vx_tumu_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vdiv_vx_tumu_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vdiv_vx_tumu_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vdiv_vx_tumu_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vdiv_vx_tumu_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vdiv_vx_tumu_rv64-3.c           | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_rv32-1.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_rv32-2.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_rv32-3.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_rv64-1.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_rv64-2.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_rv64-3.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vdivu_vx_tum_rv64-3.c           | 160 ++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv32-1.c          | 157 ++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv32-2.c          | 157 ++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv32-3.c          | 157 ++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv64-1.c          | 160 ++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv64-2.c          | 160 ++++++
 .../riscv/rvv/base/vdivu_vx_tumu_rv64-3.c          | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-3.c           | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-3.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-1.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-2.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-3.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-1.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-2.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-3.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vmaxu_vx_tum_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vmaxu_vx_tum_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vmaxu_vx_tum_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vmaxu_vx_tum_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vmaxu_vx_tum_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vmaxu_vx_tum_rv64-3.c           | 160 ++++++
 .../riscv/rvv/base/vmaxu_vx_tumu_rv32-1.c          | 157 ++++++
 .../riscv/rvv/base/vmaxu_vx_tumu_rv32-2.c          | 157 ++++++
 .../riscv/rvv/base/vmaxu_vx_tumu_rv32-3.c          | 157 ++++++
 .../riscv/rvv/base/vmaxu_vx_tumu_rv64-1.c          | 160 ++++++
 .../riscv/rvv/base/vmaxu_vx_tumu_rv64-2.c          | 160 ++++++
 .../riscv/rvv/base/vmaxu_vx_tumu_rv64-3.c          | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-1.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-2.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-3.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-1.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-2.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-3.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_rv32-1.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_rv32-2.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_rv32-3.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_rv64-1.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_rv64-2.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_rv64-3.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vmin_vx_tumu_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vmin_vx_tumu_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vmin_vx_tumu_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vmin_vx_tumu_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vmin_vx_tumu_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vmin_vx_tumu_rv64-3.c           | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-3.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_rv32-1.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_rv32-2.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_rv32-3.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_rv64-1.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_rv64-2.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_rv64-3.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vminu_vx_tum_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vminu_vx_tum_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vminu_vx_tum_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vminu_vx_tum_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vminu_vx_tum_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vminu_vx_tum_rv64-3.c           | 160 ++++++
 .../riscv/rvv/base/vminu_vx_tumu_rv32-1.c          | 157 ++++++
 .../riscv/rvv/base/vminu_vx_tumu_rv32-2.c          | 157 ++++++
 .../riscv/rvv/base/vminu_vx_tumu_rv32-3.c          | 157 ++++++
 .../riscv/rvv/base/vminu_vx_tumu_rv64-1.c          | 160 ++++++
 .../riscv/rvv/base/vminu_vx_tumu_rv64-2.c          | 160 ++++++
 .../riscv/rvv/base/vminu_vx_tumu_rv64-3.c          | 160 ++++++
 .../gcc.target/riscv/rvv/base/vmul_vv-1.c          | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv-2.c          | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv-3.c          | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_m-1.c        | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_m-2.c        | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_m-3.c        | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_mu-1.c       | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_mu-2.c       | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_mu-3.c       | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tu-1.c       | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tu-2.c       | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tu-3.c       | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tum-1.c      | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tum-2.c      | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tum-3.c      | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tumu-1.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tumu-2.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vv_tumu-3.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_rv32-1.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_rv32-2.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_rv32-3.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_rv64-1.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_rv64-2.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_rv64-3.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-3.c | 292 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv32-1.c           | 289 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv32-2.c           | 289 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv32-3.c           | 289 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv64-1.c           | 292 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv64-2.c           | 292 +++++++++++
 .../riscv/rvv/base/vmul_vx_tumu_rv64-3.c           | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_m_rv32-1.c    | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_m_rv32-2.c    | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_m_rv32-3.c    | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_m_rv64-1.c    | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_m_rv64-2.c    | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_m_rv64-3.c    | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_rv32-1.c      | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_rv32-2.c      | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_rv32-3.c      | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_rv64-1.c      | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_rv64-2.c      | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_rv64-3.c      | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-3.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c   | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c   | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c     | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c     | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vrem_vx_tumu_rv64-3.c           | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c  | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c  | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c    | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c    | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c | 157 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c | 160 ++++++
 .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c | 160 ++++++
 .../riscv/rvv/base/vremu_vx_tum_rv32-1.c           | 157 ++++++
 .../riscv/rvv/base/vremu_vx_tum_rv32-2.c           | 157 ++++++
 .../riscv/rvv/base/vremu_vx_tum_rv32-3.c           | 157 ++++++
 .../riscv/rvv/base/vremu_vx_tum_rv64-1.c           | 160 ++++++
 .../riscv/rvv/base/vremu_vx_tum_rv64-2.c           | 160 ++++++
 .../riscv/rvv/base/vremu_vx_tum_rv64-3.c           | 160 ++++++
 .../riscv/rvv/base/vremu_vx_tumu_rv32-1.c          | 157 ++++++
 .../riscv/rvv/base/vremu_vx_tumu_rv32-2.c          | 157 ++++++
 .../riscv/rvv/base/vremu_vx_tumu_rv32-3.c          | 157 ++++++
 .../riscv/rvv/base/vremu_vx_tumu_rv64-1.c          | 160 ++++++
 .../riscv/rvv/base/vremu_vx_tumu_rv64-2.c          | 160 ++++++
 .../riscv/rvv/base/vremu_vx_tumu_rv64-3.c          | 160 ++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_rv32-1.c    | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_rv32-2.c    | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_rv32-3.c    | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_rv64-1.c    | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_rv64-2.c    | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_rv64-3.c    | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.c | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-1.c           | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-2.c           | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-3.c           | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-1.c           | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-2.c           | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-3.c           | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-1.c          | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-2.c          | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-3.c          | 289 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-1.c          | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-2.c          | 292 +++++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-3.c          | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c | 292 +++++++++++
 .../riscv/rvv/base/vsub_vx_tumu_rv32-1.c           | 289 +++++++++++
 .../riscv/rvv/base/vsub_vx_tumu_rv32-2.c           | 289 +++++++++++
 .../riscv/rvv/base/vsub_vx_tumu_rv32-3.c           | 289 +++++++++++
 .../riscv/rvv/base/vsub_vx_tumu_rv64-1.c           | 292 +++++++++++
 .../riscv/rvv/base/vsub_vx_tumu_rv64-2.c           | 292 +++++++++++
 .../riscv/rvv/base/vsub_vx_tumu_rv64-3.c           | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c   | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c   | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c     | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c     | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c  | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c  | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c | 289 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c | 292 +++++++++++
 .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c | 292 +++++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv32-1.c           | 289 +++++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv32-2.c           | 289 +++++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv32-3.c           | 289 +++++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv64-1.c           | 292 +++++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv64-2.c           | 292 +++++++++++
 .../riscv/rvv/base/vxor_vx_tumu_rv64-3.c           | 292 +++++++++++
 gcc/tree-vect-stmts.cc                             |  14 +
 1132 files changed, 204141 insertions(+), 17566 deletions(-)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-1.C => vadd_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-2.C => vadd_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-3.C => vadd_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-1.C => vadd_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-2.C => vadd_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-3.C => vadd_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-1.C => vadd_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-2.C => vadd_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-3.C => vadd_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-1.C => vadd_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-2.C => vadd_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-3.C => vadd_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-1.C => vadd_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-2.C => vadd_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-3.C => vadd_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-1.C => vadd_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-2.C => vadd_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-3.C => vadd_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-1.C => vadd_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-2.C => vadd_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-3.C => vadd_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-1.C => vadd_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-2.C => vadd_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-3.C => vadd_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-1.C => vand_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-2.C => vand_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-3.C => vand_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-1.C => vand_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-2.C => vand_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-3.C => vand_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-1.C => vand_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-2.C => vand_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-3.C => vand_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-1.C => vand_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-2.C => vand_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-3.C => vand_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-1.C => vand_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-2.C => vand_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-3.C => vand_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-1.C => vand_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-2.C => vand_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-3.C => vand_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-1.C => vand_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-2.C => vand_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-3.C => vand_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-1.C => vand_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-2.C => vand_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-3.C => vand_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv64- [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-1.C => vdivu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-2.C => vdivu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-3.C => vdivu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-1.C => vdivu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-2.C => vdivu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-3.C => vdivu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-1.C => vdivu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-2.C => vdivu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-3.C => vdivu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-1.C => vdivu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-2.C => vdivu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-3.C => vdivu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-1.C => vmax_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-2.C => vmax_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-3.C => vmax_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-1.C => vmax_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-2.C => vmax_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-3.C => vmax_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-1.C => vmax_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-2.C => vmax_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-3.C => vmax_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-1.C => vmax_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-2.C => vmax_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-3.C => vmax_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-1.C => vmax_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-2.C => vmax_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-3.C => vmax_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-1.C => vmax_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-2.C => vmax_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-3.C => vmax_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-1.C => vmax_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-2.C => vmax_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-3.C => vmax_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-1.C => vmax_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-2.C => vmax_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-3.C => vmax_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv64- [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-1.C => vmin_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-2.C => vmin_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-3.C => vmin_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-1.C => vmin_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-2.C => vmin_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-3.C => vmin_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-1.C => vmin_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-2.C => vmin_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-3.C => vmin_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-1.C => vmin_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-2.C => vmin_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-3.C => vmin_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-1.C => vmin_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-2.C => vmin_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-3.C => vmin_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-1.C => vmin_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-2.C => vmin_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-3.C => vmin_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-1.C => vmin_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-2.C => vmin_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-3.C => vmin_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-1.C => vmin_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-2.C => vmin_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-3.C => vmin_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-1.C => vminu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-2.C => vminu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-3.C => vminu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-1.C => vminu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-2.C => vminu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-3.C => vminu_vx_mu_rv64- [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-1.C => vminu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-2.C => vminu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-3.C => vminu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-1.C => vminu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-2.C => vminu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-3.C => vminu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-1.C => vminu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-2.C => vminu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-3.C => vminu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-1.C => vminu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-2.C => vminu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-3.C => vminu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-1.C => vminu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-2.C => vminu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-3.C => vminu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-1.C => vminu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-2.C => vminu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-3.C => vminu_vx_tumu_r [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv32-1.C} (61%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv32-2.C} (62%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv32-3.C} (61%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv64-1.C} (62%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv64-2.C} (64%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv64-3.C} (62%)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv32-1.C} (50%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv32-2.C} (51%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv32-3.C} (50%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv64-1.C} (52%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv64-2.C} (53%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv64-3.C} (52%)
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-1.C => vor_vx_tum_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-2.C => vor_vx_tum_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-3.C => vor_vx_tum_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-1.C => vor_vx_tum_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-2.C => vor_vx_tum_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-3.C => vor_vx_tum_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-1.C => vor_vx_tumu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-2.C => vor_vx_tumu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-3.C => vor_vx_tumu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-1.C => vor_vx_tumu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-2.C => vor_vx_tumu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-3.C => vor_vx_tumu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-1.C => vrem_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-2.C => vrem_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-3.C => vrem_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-1.C => vrem_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-2.C => vrem_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-3.C => vrem_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-1.C => vrem_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-2.C => vrem_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-3.C => vrem_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-1.C => vrem_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-2.C => vrem_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-3.C => vrem_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-1.C => vrem_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-2.C => vrem_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-3.C => vrem_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-1.C => vrem_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-2.C => vrem_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-3.C => vrem_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-1.C => vrem_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-2.C => vrem_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-3.C => vrem_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-1.C => vrem_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-2.C => vrem_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-3.C => vrem_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-1.C => vremu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-2.C => vremu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-3.C => vremu_vx_mu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-1.C => vremu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-2.C => vremu_vx_mu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-3.C => vremu_vx_mu_rv64- [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-1.C => vremu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-2.C => vremu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-3.C => vremu_vx_tu_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-1.C => vremu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-2.C => vremu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-3.C => vremu_vx_tu_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-1.C => vremu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-2.C => vremu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-3.C => vremu_vx_tum_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-1.C => vremu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-2.C => vremu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-3.C => vremu_vx_tum_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-1.C => vremu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-2.C => vremu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-3.C => vremu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-1.C => vremu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-2.C => vremu_vx_tumu_r [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-3.C => vremu_vx_tumu_r [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-1.C => vsub_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-2.C => vsub_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-3.C => vsub_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-1.C => vsub_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-2.C => vsub_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-3.C => vsub_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-1.C => vsub_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-2.C => vsub_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-3.C => vsub_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-1.C => vsub_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-2.C => vsub_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-3.C => vsub_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-1.C => vsub_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-2.C => vsub_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-3.C => vsub_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-1.C => vsub_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-2.C => vsub_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-3.C => vsub_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-1.C => vsub_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-2.C => vsub_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-3.C => vsub_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-1.C => vsub_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-2.C => vsub_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-3.C => vsub_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-1.C => vxor_vx_mu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-2.C => vxor_vx_mu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-3.C => vxor_vx_mu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-1.C => vxor_vx_mu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-2.C => vxor_vx_mu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-3.C => vxor_vx_mu_rv64-3. [...]
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-1.C => vxor_vx_tu_rv32-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-2.C => vxor_vx_tu_rv32-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-3.C => vxor_vx_tu_rv32-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-1.C => vxor_vx_tu_rv64-1. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-2.C => vxor_vx_tu_rv64-2. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-3.C => vxor_vx_tu_rv64-3. [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-1.C => vxor_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-2.C => vxor_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-3.C => vxor_vx_tum_rv32- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-1.C => vxor_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-2.C => vxor_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-3.C => vxor_vx_tum_rv64- [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-1.C => vxor_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-2.C => vxor_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-3.C => vxor_vx_tumu_rv3 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-1.C => vxor_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-2.C => vxor_vx_tumu_rv6 [...]
 copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-3.C => vxor_vx_tumu_rv6 [...]
 create mode 100644 gcc/testsuite/gcc.target/i386/pr108724.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-47.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-49.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-51.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-52.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-53.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-54.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-55.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-57.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-58.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-59.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-60.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-61.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-63.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-65.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-66.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-67.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-69.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-70.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-71.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-72.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-73.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-75.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-76.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-77.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-78.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-80.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-81.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-82.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-83.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-85.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-86.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-87.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-88.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-89.c
 copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-91.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-92.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-93.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-94.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-95.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-3.c
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[Tcwg-commits] [gcc] branch master updated (2a37a4a3cbf -> edfc4402504)