This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository gcc.
from d14a5db1247 aarch64: Avoid INS-(W|X)ZR instructions when optimising for speed new 9e2aaaba47c RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G [...] new 04cfb719574 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case [...] new 2d90c95f77a RISC-V: Add test for vec_duplicate + vaaddu.vv combine case [...] new e184f73d91b RISC-V: Allow VLS DImode for sat_op vx DImode pattern new bd9fc3a53ff RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode new b441d735c09 [RISC-V] Fix wrong CFA during stack probe
The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/autovec-opt.md | 62 +++++++ gcc/config/riscv/riscv.cc | 31 +++- gcc/config/riscv/vector.md | 30 ++-- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c | 2 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 56 ++++-- .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 +++++++++++++++++++++ .../{vx_vmin-run-1-u16.c => vx_vaadd-run-1-u16.c} | 4 +- .../{vx_vmin-run-1-u32.c => vx_vaadd-run-1-u32.c} | 4 +- .../{vx_vmin-run-1-u64.c => vx_vaadd-run-1-u64.c} | 6 +- .../{vx_vmin-run-1-u8.c => vx_vaadd-run-1-u8.c} | 4 +- 33 files changed, 387 insertions(+), 42 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vmin-run-1-u16.c => vx_v [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vmin-run-1-u32.c => vx_v [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vmin-run-1-u64.c => vx_v [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vmin-run-1-u8.c => vx_va [...]