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from 5027779 [AMDGPU] Move reserved vgpr count for trap handler usage to S [...] new 6568fd1 test: remove some bleeding whitespace new d632f47 tests: tweak MIR for ARM tests to correct MI issues
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Summary of changes: test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir | 67 ++++++++++++++------------- test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir | 59 +++++++++++------------ 2 files changed, 64 insertions(+), 62 deletions(-)