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from 8f2f7aabcef RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4 new 17be00916e5 RISC-V: Support IMM for operand 0 of ussub pattern
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Summary of changes: gcc/config/riscv/riscv.cc | 46 +++++++++++++++++- gcc/config/riscv/riscv.md | 2 +- gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++ .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-1.c} | 10 ++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-1_1.c} | 10 ++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-1_2.c} | 10 ++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-2.c} | 13 +++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-2_1.c} | 13 +++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-2_2.c} | 14 ++++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-3.c} | 12 +++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-3_1.c} | 13 +++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-3_2.c} | 14 ++++-- .../riscv/{sat_u_sub-1.c => sat_u_sub_imm-4.c} | 11 +++-- .../gcc.target/riscv/sat_u_sub_imm-run-1.c | 56 ++++++++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-run-2.c | 56 ++++++++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-run-3.c | 55 +++++++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-run-4.c | 48 +++++++++++++++++++ 17 files changed, 344 insertions(+), 49 deletions(-) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-1.c} (71%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-1_1.c} (71%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-1_2.c} (71%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-2.c} (64%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-2_1.c} (63%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-2_2.c} (58%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-3.c} (66%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-3_1.c} (61%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-3_2.c} (56%) copy gcc/testsuite/gcc.target/riscv/{sat_u_sub-1.c => sat_u_sub_imm-4.c} (69%) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-4.c