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from 80d9802d923 [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction new aba0e1b1de9 [AArch64][v8.5A] Add Armv8.5-A random number instructions new c3edf1b3445 [AArch64][v8.5A] Add speculation restriction system registers
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Summary of changes: include/llvm/Support/AArch64TargetParser.def | 1 + include/llvm/Support/TargetParser.h | 1 + lib/Target/AArch64/AArch64.td | 10 +++- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +- lib/Target/AArch64/AArch64Subtarget.h | 4 ++ lib/Target/AArch64/AArch64SystemOperands.td | 27 +++++++++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 3 +- test/MC/AArch64/armv8.5a-rand-error.s | 17 ++++++ test/MC/AArch64/armv8.5a-rand.s | 14 +++++ test/MC/AArch64/armv8.5a-specrestrict-error.s | 10 ++++ test/MC/AArch64/armv8.5a-specrestrict.s | 69 ++++++++++++++++++++++ test/MC/Disassembler/AArch64/armv8.5a-rand.txt | 12 ++++ .../Disassembler/AArch64/armv8.5a-specrestrict.txt | 52 ++++++++++++++++ unittests/Support/TargetParserTest.cpp | 3 +- 15 files changed, 222 insertions(+), 6 deletions(-) create mode 100644 test/MC/AArch64/armv8.5a-rand-error.s create mode 100644 test/MC/AArch64/armv8.5a-rand.s create mode 100644 test/MC/AArch64/armv8.5a-specrestrict-error.s create mode 100644 test/MC/AArch64/armv8.5a-specrestrict.s create mode 100644 test/MC/Disassembler/AArch64/armv8.5a-rand.txt create mode 100644 test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt