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from 06bac6c858a [LV] Support vectorization of interleave-groups that requir [...] new b1ebaf21d0d [IndVars] Strengthen restricton in rewriteLoopExitValues new 5ab552691a8 [AMDGPU] support image load/store a16
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Summary of changes: lib/Target/AMDGPU/SIISelLowering.cpp | 6 +- lib/Transforms/Scalar/IndVarSimplify.cpp | 35 +- test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll | 530 +++++++++++++++++++++ .../AMDGPU/llvm.amdgcn.image.load.a16.d16.ll | 128 +++++ test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll | 128 +++++ .../AMDGPU/llvm.amdgcn.image.store.a16.d16.ll | 140 ++++++ test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll | 128 +++++ test/MC/AMDGPU/mimg.s | 88 ++++ test/Transforms/IndVarSimplify/dont-recompute.ll | 26 + 9 files changed, 1179 insertions(+), 30 deletions(-) create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll