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from 96686b3fcd1 Daily bump. new 0757d3660c1 rs6000/test: Add -fno-vect-cost-model to conv-vectorize-[12].c new 80029561822 Fix PR96127 new 0c1d1c01039 gcc-changelog: Fix typo in output new bf592b2ff77 AArch64: Add flags in built-in functions [PR94442] new 7efc03fd2cb __builtin_shuffle sometimes should produce zip1 rather than [...] new c9c87e6f9c7 vector creation from two parts of two vectors produces TBL [...]
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Summary of changes: contrib/gcc-changelog/git_update_version.py | 2 +- gcc/config/aarch64/aarch64-builtins.c | 131 +-- gcc/config/aarch64/aarch64-simd-builtins.def | 1014 ++++++++++---------- gcc/config/aarch64/aarch64-simd.md | 2 +- gcc/config/aarch64/aarch64.c | 134 +++ gcc/config/aarch64/geniterators.sh | 4 +- gcc/config/s390/s390.c | 15 +- gcc/config/s390/s390.md | 4 +- gcc/testsuite/gcc.target/aarch64/vdup_n_3.c | 16 + gcc/testsuite/gcc.target/aarch64/vins-1.c | 23 + gcc/testsuite/gcc.target/aarch64/vins-2.c | 23 + gcc/testsuite/gcc.target/aarch64/vins-3.c | 23 + gcc/testsuite/gcc.target/aarch64/vzip_1.c | 12 + gcc/testsuite/gcc.target/aarch64/vzip_2.c | 13 + gcc/testsuite/gcc.target/aarch64/vzip_3.c | 13 + gcc/testsuite/gcc.target/aarch64/vzip_4.c | 13 + .../gcc.target/powerpc/conv-vectorize-1.c | 2 +- .../gcc.target/powerpc/conv-vectorize-2.c | 2 +- .../pr92085-2.c => gcc.target/s390/pr96127.c} | 2 +- 19 files changed, 868 insertions(+), 580 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vdup_n_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vins-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vins-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vins-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vzip_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vzip_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vzip_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vzip_4.c copy gcc/testsuite/{gcc.dg/tree-ssa/pr92085-2.c => gcc.target/s390/pr96127.c} (77%)