[Tcwg-commits] [gcc] branch master updated (4fd0cfd87b1 -> 2cd7cbaf51f)

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unknown user pushed a change to branch master in repository gcc.

from 4fd0cfd87b1 libstdc++: Change www.unix.org to unix.org new e09418f21dd RISC-V: Add fixed-point support new 71a1c2c67aa RISC-V: Add vssrl.vx C API tests new 13907f4bd2e RISC-V: Add vssrl.vv C API tests new 4e00937ec3e RISC-V: Add vssra.vx C API tests new 5ca5ca30b6a RISC-V: Add vssra.vv C API tests new bbb168daecf RISC-V: Add vsmul.vx C API tests new c156e8d7bcf RISC-V: Add vsmul.vv C API tests new 367a01e6a06 RISC-V: Add vnclip C API tests new 1580eda6c3d RISC-V: Add vasubu.vx C API tests new 193a125c3fe RISC-V: Add vasubu.vv C API tests new 48e24473fe1 RISC-V: Add vasub.vx C API tests new 4432ef4eca4 RISC-V: Add vasub.vv C API tests new 6ad0002f1e3 RISC-V: Add vaaddu.vx C API tests new 119e5d9aff3 RISC-V: Add vaaddu.vv C api tests new 5898e1f333b RISC-V: Add vaadd.vx C api tests new e85cb86e338 RISC-V: Add vaadd.vv C api tests new b7795fb143c RISC-V: Add vssrl.vx C++ API tests new 02b0325269b RISC-V: Add vssrl.vv C++ API tests new 7326a694da9 RISC-V: Add vssra.vx C++ API tests new 49e53882081 RISC-V: Add vssra.vv C++ API tests new 73dea8e6426 RISC-V: Add vsmul.vx C++ API tests new 7302972bcd5 RISC-V: Add vsmul.vv C++ API tests new 0906435e2b6 RISC-V: Add vnclip C++ API tests new 90ea2d28d47 RISC-V: Add vasubu.vx C++ API tests new 1a8c69e7ea6 RISC-V: Add vasubu.vv C++ API tests new 3d65ea07b47 RISC-V: Add vasub.vx C++ API tests new ff4d996600b RISC-V: Add vasub.vv C++ api tests new 2ec75330230 RISC-V: Add vaaddu.vx C++ Api tests new 0b1f45786f4 RISC-V: Add vaaddu.vv C++ api tests new e8a0c9e9d41 RISC-V: Add vaadd.vx C++ API tests new 2cd7cbaf51f RISC-V: Add vaadd.vv C++ API tests

The 31 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/riscv-vector-builtins-bases.cc | 59 ++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 12 +- .../riscv/riscv-vector-builtins-functions.def | 18 ++ gcc/config/riscv/vector-iterators.md | 32 ++- gcc/config/riscv/vector.md | 238 +++++++++++++++- .../g++.target/riscv/rvv/base/vaadd_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-3.C | 314 +++++++++++++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C | 314 +++++++++++++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-2.C | 157 +++++++++++ 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.../g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-1.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-2.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-3.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_mu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_mu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_mu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tum-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tum-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tum-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-1.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-2.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-3.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-1.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-2.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-3.C | 216 ++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C | 111 ++++++++ .../g++.target/riscv/rvv/base/vsmul_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vx-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vx-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssra_vx_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/binop_vx_constraint-122.c | 21 ++ .../gcc.target/riscv/rvv/base/vaadd_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vaaddu_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasub_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c | 111 ++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsmul_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c | 160 +++++++++++ 765 files changed, 124837 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-2.C create mode 100644 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gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-3.C create mode 100644 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