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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Os in repository toolchain/ci/llvm-project.
from f85d63a5583 Fix wrong devirtualization when the final overrider in one [...] adds e11d70cfe7e Make quick-append.test resilient to running in paths with ' [...] adds 72e9e378c54 [Sema] Remove a -Wrange warning from -Wall adds dd50560c38d MSVC Buggy version detection: turn pre-processor error into [...] adds cbd4815dec1 [AArch64] -fpatchable-function-entry=N,0: place patch label [...] adds 674ec1eb166 [libcxxabi] Insert padding in __cxa_exception struct for co [...] adds 2b54b8b994b [Concepts] Instantiate invented template type parameter typ [...] adds c822edc11bf Revert "[Concepts] Instantiate invented template type param [...] adds 1ac1c4b4850 [Concepts] Instantiate invented template type parameter typ [...] adds 4e9209ab592 [RISCV] Scheduler description for the Rocket core adds 94c79ce5740 Revert "[AMDGPU] Invert the handling of skip insertion." adds b905b85eedf [BPF] fix a bug in BPFMISimplifyPatchable pass with -O0 adds 5cca13d43b7 AMDGPU/R600: Emit rodata in text segment adds fa51929f03f R600: Fix failing testcase adds 7ad47b46b55 [clang-tidy] Fixed crash 44745 in readability-else-after-return adds 4ea9a4aba4a Declare __builtin_strlen in StringRef.h as constexpr adds d2a710ea784 Actually, don't try to use __builtin_strlen in StringRef.h [...] adds 165a6367631 [libcxxabi] Fix layout of __cxa_exception for win64 adds db51c41a646 [ELF] Decrease alignment of ThunkSection on 64-bit targets [...] adds 852b37f83b2 [LLD][ELF][ARM][AArch64] Only round up ThunkSection Size wh [...] adds 5f6fec2404c AMDGPU: Fix handling of infinite loops in fragment shaders adds ca6b341bd5d [libcxx] [Windows] Store the lconv struct returned from loc [...] adds 2d9954dd824 Add -Wrange-loop-analysis changes to ReleaseNotes adds 300cbdc59da PR44761: Fix fallback to later tiebreakers if two non-templ [...] adds 7a94fc09d17 PR44721: Don't consider overloaded operators for built-in c [...] adds 8f19f984f29 [Concepts] Add missing CXXThisScope to function template co [...] adds b833e0c5f11 PR44786: Don't assert when profiling <=> expressions. adds 211aa5bf59e [mlir] Mark the MLIR tools for installation in CMake adds 0b8a540dff8 [AArch64][ARM] Always expand ordered vector reductions (PR44600) adds 99c6a4ea920 [ARM] Expand vector reduction intrinsics on soft float adds 8195a96595b [ARM][VecReduce] Force expand vector_reduce_fmin adds b4efc29f1cc Update for Clang 10 release notes in order to have referenc [...] adds 4c96b369a07 [X86] -fpatchable-function-entry=N,0: place patch label aft [...] adds fd271fd64a2 Don't warn about missing declarations for partial template [...] adds 5288d7af5bc [OpenMP][OMPT] fix reduction test for 32-bit x86 adds 424babb89ad [LLD] Add release notes for MinGW for the 10.x branch adds 0f99f678feb [docs] Add LLVM/LLDB release notes for the 10.x branch for [...] adds 7e518f3159b [clang] Add release notes for the 10.x branch for things I've done adds d5361190993 [libcxx] Add release notes for the 10.x branch for things I [...] adds c32d809e9ca [TSan] Ensure we can compile the runtime with older SDKs adds d0104a59619 Make llvm::crc32() work also for input sizes larger than 32 bits. adds cbec01fe058 [clangd] Add workaround for GCC5 host compilers. NFC. adds 22633f85bb7 [LLDB] Fix compilation with GCC 5 adds 02420968fcc Fix x86 32bits MLIR build (NFC) adds c0c5ab30179 [LV] Fix predication for branches with matching true and fa [...] adds 96ed02ddeeb [Concepts] Fix incorrect check when instantiating abbreviat [...] adds ed368ba5a96 StringRef.h: __builtin_strlen seems to exist in VS 2017 MSV [...] adds 7996b49053f Revert "[ARM] Improve codegen of volatile load/store of i64" adds 9db3e5d5156 [InstCombine] Fix infinite loop in min/max load/store bitca [...] adds d65ef4321e6 [InstCombine] Add test for -expensive-combines option; NFC adds d9b836dc6f7 [InstCombine] Support disabling expensive combines in opt adds fc12083cbc5 [InstCombine] Fix infinite min/max canonicalization loop (PR44541) adds 4ea0b397582 PowerPC release notes adds a124bebdd5f [ARM] Fix non-determenistic behaviour adds e2c0c70101a [cmake] Fix clang builds with BUILD_SHARED=ON and CLANG_LIN [...] adds 720870ee60a [analyzer] Fix a couple of bugs in HTML report generation. adds 3f4ba96a59a [BPF] disable ReduceLoadWidth during SelectionDag phase adds 8b8a4834a4b [X86] Use MVT::i8 instead of MVT::i64 for shift amount in B [...] adds 84cda4cceab [clang-tidy] Fix false positive for cppcoreguidelines-init- [...] adds b73942dbc14 AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead [...] adds b8fead783fa [AArch64] Add option to enable/disable load-store renaming. adds 793d643f6d6 [Clang] Remove unused #pragma clang __debug handle_crash adds 64515b35844 [analyzer] Add 10.0.0 release notes. adds 4759c6ef8b4 [Support] When using SEH, create a impl instance for CrashR [...] adds 0e1c734fa5b Re-land "[Clang][Driver] Remove -M group options ..." and " [...] adds f23caecc090 ReleaseNotes / external projects: Zig adds 699e2a6c555 Prefer __vector over vector keyword for altivec adds 4e6ec0fff65 IR Linking: Support merging Warning+Max module metadata flags adds dbe9c3a82dd [Support] Don't modify the current EH context during stack [...] adds aeba7ba9f3d Add SystemZ release notes
No new revisions were added by this update.
Summary of changes: .../cppcoreguidelines/InitVariablesCheck.cpp | 14 +- .../readability/ElseAfterReturnCheck.cpp | 4 + clang-tools-extra/clangd/Hover.cpp | 8 +- .../checkers/cppcoreguidelines-init-variables.cpp | 6 + .../checkers/readability-else-after-return.cpp | 13 + clang/docs/ReleaseNotes.rst | 51 +- clang/include/clang/Basic/DiagnosticGroups.td | 8 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 6 +- clang/include/clang/Driver/CC1Options.td | 2 + clang/include/clang/Lex/PreprocessorOptions.h | 3 + clang/lib/AST/StmtProfile.cpp | 4 +- clang/lib/Driver/Compilation.cpp | 13 +- clang/lib/Driver/ToolChains/Clang.cpp | 5 + clang/lib/Frontend/CompilerInvocation.cpp | 1 + clang/lib/Lex/Lexer.cpp | 4 +- clang/lib/Lex/Pragma.cpp | 33 +- clang/lib/Sema/SemaConcept.cpp | 7 + clang/lib/Sema/SemaDecl.cpp | 1 + clang/lib/Sema/SemaDeclCXX.cpp | 29 +- clang/lib/Sema/SemaOverload.cpp | 14 +- clang/lib/Sema/SemaTemplateInstantiate.cpp | 129 ++ clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 88 +- clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp | 11 +- clang/test/Analysis/html_diagnostics/td-hotfix.c | 31 + .../html_diagnostics/variable-popups-macro.c | 28 + .../html_diagnostics/variable-popups-multiple.c | 29 + .../html_diagnostics/variable-popups-simple.c | 23 + .../class.compare/class.compare.default/p3.cpp | 12 + .../CXX/over/over.match/over.match.best/p2.cpp | 16 + ...{crash-report.c => crash-report-with-asserts.c} | 35 +- clang/test/Driver/crash-report.c | 25 +- clang/test/Misc/warning-wall.c | 5 +- clang/test/SemaCXX/cxx2a-three-way-comparison.cpp | 9 + .../SemaCXX/warn-missing-variable-declarations.cpp | 2 + clang/test/SemaCXX/warn-range-loop-analysis.cpp | 2 +- .../instantiate-abbreviated-template.cpp | 33 + .../SemaTemplate/instantiate-requires-clause.cpp | 11 +- clang/tools/clang-shlib/CMakeLists.txt | 17 +- compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp | 9 +- libcxx/docs/ReleaseNotes.rst | 5 + libcxx/include/support/win32/locale_win32.h | 73 +- libcxx/src/support/win32/locale_win32.cpp | 8 +- libcxxabi/src/cxa_exception.h | 53 +- lld/ELF/Relocations.cpp | 31 + lld/ELF/SyntheticSections.cpp | 11 +- lld/ELF/SyntheticSections.h | 4 + lld/docs/ReleaseNotes.rst | 28 +- lld/test/ELF/aarch64-call26-thunk.s | 10 +- .../ELF/aarch64-cortex-a53-843419-thunk-align.s | 74 + lld/test/ELF/aarch64-cortex-a53-843419-thunk.s | 13 +- lld/test/ELF/aarch64-jump26-thunk.s | 10 +- lld/test/ELF/aarch64-thunk-pi.s | 12 +- lld/test/ELF/aarch64-thunk-script.s | 18 +- lld/test/ELF/arm-fix-cortex-a8-thunk-align.s | 41 + lld/test/ELF/arm-fix-cortex-a8-thunk.s | 18 +- lld/test/ELF/ppc64-dtprel.s | 8 +- lld/test/ELF/ppc64-ifunc.s | 22 +- lld/test/ELF/ppc64-long-branch.s | 4 +- lld/test/ELF/ppc64-tls-gd.s | 18 +- lld/test/ELF/ppc64-toc-restore.s | 4 +- lldb/source/DataFormatters/FormatCache.cpp | 4 + lldb/source/DataFormatters/LanguageCategory.cpp | 4 + lldb/source/Interpreter/CommandAlias.cpp | 3 +- lldb/source/Interpreter/Options.cpp | 4 +- llvm/cmake/modules/CheckCompilerVersion.cmake | 14 + llvm/docs/LangRef.rst | 4 +- llvm/docs/ReleaseNotes.rst | 58 +- llvm/include/llvm/ADT/StringRef.h | 3 +- llvm/include/llvm/CodeGen/AsmPrinter.h | 3 +- llvm/include/llvm/Support/CrashRecoveryContext.h | 4 - llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 8 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 4 +- llvm/lib/CodeGen/TypePromotion.cpp | 12 +- llvm/lib/Linker/IRMover.cpp | 70 +- llvm/lib/Support/CRC.cpp | 10 +- llvm/lib/Support/CrashRecoveryContext.cpp | 68 +- llvm/lib/Support/Windows/Signals.inc | 8 +- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 20 + .../Target/AArch64/AArch64LoadStoreOptimizer.cpp | 7 + .../Target/AArch64/AArch64TargetTransformInfo.h | 16 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 3 - llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 - .../AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp | 79 +- llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 - llvm/lib/Target/AMDGPU/CaymanInstructions.td | 4 +- llvm/lib/Target/AMDGPU/EvergreenInstructions.td | 3 +- llvm/lib/Target/AMDGPU/R600Instructions.td | 7 +- llvm/lib/Target/AMDGPU/SIInsertSkips.cpp | 5 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 10 +- .../Target/AMDGPU/SIRemoveShortExecBranches.cpp | 158 -- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 18 - llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 49 - llvm/lib/Target/ARM/ARMISelLowering.cpp | 57 +- llvm/lib/Target/ARM/ARMISelLowering.h | 8 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 27 - llvm/lib/Target/ARM/ARMInstrThumb2.td | 9 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 21 +- llvm/lib/Target/BPF/BPFISelLowering.h | 13 + llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp | 7 +- llvm/lib/Target/RISCV/RISCV.td | 9 + llvm/lib/Target/RISCV/RISCVInstrFormats.td | 3 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 109 +- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 64 +- llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 156 +- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 69 +- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 72 +- llvm/lib/Target/RISCV/RISCVInstrInfoM.td | 39 +- llvm/lib/Target/RISCV/RISCVSchedRocket32.td | 213 ++ llvm/lib/Target/RISCV/RISCVSchedRocket64.td | 214 ++ llvm/lib/Target/RISCV/RISCVSchedule.td | 138 ++ llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86MCInstLower.cpp | 19 + .../InstCombine/InstCombineLoadStoreAlloca.cpp | 5 + .../Transforms/InstCombine/InstCombineSelect.cpp | 6 + .../InstCombine/InstructionCombining.cpp | 3 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 2 +- llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll | 2 +- llvm/test/CodeGen/AArch64/arm64-abi_align.ll | 4 +- llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll | 2 +- .../CodeGen/AArch64/machine-outliner-remarks.ll | 6 +- llvm/test/CodeGen/AArch64/machine-outliner.ll | 4 +- .../AArch64/patchable-function-entry-bti.ll | 49 +- .../AArch64/stp-opt-with-renaming-debug.mir | 2 +- .../stp-opt-with-renaming-reserved-regs.mir | 8 +- .../test/CodeGen/AArch64/stp-opt-with-renaming.mir | 8 +- .../AArch64/vecreduce-fadd-legalization-strict.ll | 128 ++ ...ation.ll => vecreduce-fmax-legalization-nan.ll} | 49 +- .../CodeGen/AArch64/vecreduce-fmax-legalization.ll | 2 +- .../AArch64/vecreduce-fmul-legalization-strict.ll | 114 + .../AMDGPU/GlobalISel/divergent-control-flow.ll | 11 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 312 ++- .../AMDGPU/atomic_optimizations_pixelshader.ll | 2 +- llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | 5 +- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 9 +- llvm/test/CodeGen/AMDGPU/call-skip.ll | 9 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 49 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 15 +- llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll | 8 +- llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll | 2 +- .../AMDGPU/divergent-branch-uniform-condition.ll | 11 +- llvm/test/CodeGen/AMDGPU/else.ll | 3 +- llvm/test/CodeGen/AMDGPU/fsqrt.ll | 38 +- llvm/test/CodeGen/AMDGPU/global-constant.ll | 6 + llvm/test/CodeGen/AMDGPU/hoist-cond.ll | 2 +- .../test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir | 2 +- llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir | 2 +- .../CodeGen/AMDGPU/insert-skips-ignored-insts.mir | 2 +- .../CodeGen/AMDGPU/insert-skips-kill-uncond.mir | 2 +- llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll | 68 + .../test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 6 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 3 +- .../CodeGen/AMDGPU/r600-constant-array-fixup.ll | 6 +- llvm/test/CodeGen/AMDGPU/ret_jump.ll | 23 +- llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll | 2 + .../si-lower-control-flow-unreachable-block.ll | 10 +- llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir | 2 +- .../CodeGen/AMDGPU/skip-branch-taildup-ret.mir | 2 +- llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll | 7 +- llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 13 +- llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll | 2 +- .../stack-pointer-offset-relative-frameindex.ll | 3 +- .../CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 5 +- llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 2 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 2 + llvm/test/CodeGen/AMDGPU/valu-i1.ll | 42 +- llvm/test/CodeGen/AMDGPU/wave32.ll | 16 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 5 +- llvm/test/CodeGen/ARM/i64_volatile_load_store.ll | 180 -- .../ARM/vecreduce-fadd-legalization-soft-float.ll | 63 + .../ARM/vecreduce-fadd-legalization-strict.ll | 166 ++ .../ARM/vecreduce-fmul-legalization-strict.ll | 166 ++ llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll | 156 ++ llvm/test/CodeGen/BPF/optnone-1.ll | 52 + llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 2264 ++++++++++++++++++++ .../CodeGen/X86/patchable-function-entry-ibt.ll | 68 +- llvm/test/CodeGen/X86/pr44812.ll | 24 + llvm/test/Linker/Inputs/module-max-warn.ll | 3 + llvm/test/Linker/module-max-warn.ll | 12 + .../Transforms/InstCombine/expensive-combines.ll | 28 + llvm/test/Transforms/InstCombine/pr44541.ll | 25 + llvm/test/Transforms/InstCombine/pr44835.ll | 29 + .../LoopVectorize/pr44488-predication.ll | 79 + llvm/test/tools/llvm-ar/quick-append.test | 18 +- llvm/unittests/Support/CRCTest.cpp | 20 + mlir/lib/Transforms/DialectConversion.cpp | 2 +- mlir/tools/mlir-cpu-runner/CMakeLists.txt | 2 +- mlir/tools/mlir-cuda-runner/CMakeLists.txt | 2 +- mlir/tools/mlir-translate/CMakeLists.txt | 2 +- .../ompt/synchronization/reduction/tree_reduce.c | 10 +- 190 files changed, 6309 insertions(+), 1285 deletions(-) create mode 100644 clang/test/Analysis/html_diagnostics/td-hotfix.c create mode 100644 clang/test/Analysis/html_diagnostics/variable-popups-macro.c create mode 100644 clang/test/Analysis/html_diagnostics/variable-popups-multiple.c create mode 100644 clang/test/Analysis/html_diagnostics/variable-popups-simple.c create mode 100644 clang/test/CXX/over/over.match/over.match.best/p2.cpp copy clang/test/Driver/{crash-report.c => crash-report-with-asserts.c} (61%) create mode 100644 clang/test/SemaTemplate/instantiate-abbreviated-template.cpp create mode 100644 lld/test/ELF/aarch64-cortex-a53-843419-thunk-align.s create mode 100644 lld/test/ELF/arm-fix-cortex-a8-thunk-align.s delete mode 100644 llvm/lib/Target/AMDGPU/SIRemoveShortExecBranches.cpp create mode 100644 llvm/lib/Target/RISCV/RISCVSchedRocket32.td create mode 100644 llvm/lib/Target/RISCV/RISCVSchedRocket64.td create mode 100644 llvm/lib/Target/RISCV/RISCVSchedule.td create mode 100644 llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll copy llvm/test/CodeGen/AArch64/{vecreduce-fmax-legalization.ll => vecreduce-fmax-l [...] create mode 100644 llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll create mode 100644 llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll delete mode 100644 llvm/test/CodeGen/ARM/i64_volatile_load_store.ll create mode 100644 llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll create mode 100644 llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll create mode 100644 llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll create mode 100644 llvm/test/CodeGen/BPF/optnone-1.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll create mode 100644 llvm/test/CodeGen/X86/pr44812.ll create mode 100644 llvm/test/Linker/Inputs/module-max-warn.ll create mode 100644 llvm/test/Linker/module-max-warn.ll create mode 100644 llvm/test/Transforms/InstCombine/expensive-combines.ll create mode 100644 llvm/test/Transforms/InstCombine/pr44541.ll create mode 100644 llvm/test/Transforms/InstCombine/pr44835.ll create mode 100644 llvm/test/Transforms/LoopVectorize/pr44488-predication.ll