[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig updated (ef85f47595a -> f01b9aa89e8)

5 Nov 2019


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig
in repository toolchain/ci/llvm-project.
from  ef85f47595a [llvm-readobj] Change errors to warnings for symbol section [...]
      adds  499c90afe90 [InstSimplify] add more tests for fcmp+select; NFC
      adds  22f9429149a [SystemZ] Add GHC calling convention
      adds  82888b78d47 [OpenCL] Fix address space for const method call from nonco [...]
      adds  ad87f244b42 [InstSimplify] add more tests for fcmp+select; NFC
      adds  659bd73d136 [InstSimplify] use FMF to improve fcmp+select fold
      adds  6bae5d16a28 [ARM] Add vrev32 NEON fp16 patterns
      adds  1c616a9266b [ARM] More MVE shuffle tests for sequences that can be conv [...]
      adds  d3ec06d2197 Revert "[LV] Apply sink-after & interleave-groups as VPlan  [...]
      adds  a3915ca9f90 gn build: add deps, see discussion on D69130
      adds  9cd13deb293 gn build: run "gn format"
      adds  4168a2e9de3 gn build: (manually) merge 51b4b17eb
      adds  d4a7855b68d [SystemZ] Fix typo
      adds  d142ec6fef9 Fix compilation warning. NFC.
      adds  b556ce39927 [IR] adjust assert when replacing undef elements in vector  [...]
      adds  91b0cad8132 [ARM] Use isFMAFasterThanFMulAndFAdd for MVE
      adds  6c5827975cf [OpenCL] Fix FileCheck pattern
      adds  03cde3a7ccd [X86] Regenerate known-signbits-vector.ll tests.
      adds  a0324e91137 SanitizerMask::bitPosToMask - fix operator precedence warni [...]
      adds  b7b170c9b46 [MachineVerifier]  Improve verification of live-in lists.
      adds  bf6744dfb24 [SystemZ]  Use LivePhysRegs instead of isCCLiveOut() in Sys [...]
      adds  0bab0538d8c [test] Use system locale for mri-utf8.test
      adds  55507110b98 [Diagnostics] Improve some error messages related to bad us [...]
      adds  1abb2c1a39f AliasSetTracker - fix uninitialized variable warnings. NFCI.
      adds  9ad9d1531b9 [X86] Convert ShrinkMode to scoped enum class. NFCI.
      adds  b80c41cd3c0 [SLP]Fix PR43799: Crash on different sizes of GEP indices.
      adds  b14ff0caecb Fix buildbots troubled by b7b170c.
      adds  9ba16615fa0 [Sema] Make helper in TreeTransform.h 'inline' instead of ' [...]
      adds  664f84e2464 [FPEnv][SelectionDAG] Refactor strict FP node construction
      adds  2c6fae179e6 ELF: Discard .ARM.exidx sections for empty functions instea [...]
      adds  ab76cfdd200 Recommit "[CodeView] Add option to disable inline line tables."
      adds  40d0d4e2335 Lower generic MASSV entries to PowerPC subtarget-specific entries
      adds  73c3137a82c Fix static analysis warnings in ARM calling convention lowering
      adds  667223c3ed6 gn build: Merge 40d0d4e2335
      adds  692b42fbb05 MCDwarfFile::DirIndex - fix uninitialized variable warning. NFCI.
      adds  67286c87854 createMCObjectStreamer - fix uninitialized variable warning. NFCI.
      adds  e1000f1d674 VirtualFileSystem - fix uninitialized variable warnings. NFCI.
      adds  a8653da4320 [X86] Fix uninitialized variable warnings. NFCI.
      adds  be6ac471f61 [ms] Fix Microsoft compatibility handling of commas in nest [...]
      adds  d8f2bff7512 [lit] Better/earlier errors when no tests are executed
      adds  bd14bb42f03 [lit] Move measurement of testing time out of Run.execute
      adds  6eca4f46912 [lldb] [Process/NetBSD] Add register info for missing regis [...]
      adds  113181e9bd0 [DAGCombine][MSP430] use shift amount threshold in DAGCombi [...]
      adds  6ff439b57f0 [SimplifyCFG] Use a (trivially) dominanting widenable branc [...]
      adds  b2b6a54f847 [X86] Add support for -mvzeroupper and -mno-vzeroupper to m [...]
      adds  8112a423a8e clang/Modules: Bring back optimization lost in 31e14f41a21f
      adds  9cc3ebf8b76 Fix warning: format specifies type 'unsigned long' but the  [...]
      adds  efad56b2be9 Remove unused variables, as suggested by @mcgov.
      adds  af11f417fc7 [demangle] NFC: get rid of NodeOrString
      adds  4312c4afd43 [AMDGPU] deduplicate tablegen predicates
      adds  adbf64ccc9e [LLDB][Python] remove ArgInfo::count
      adds  8bbf2e37167 [OPENMP50]Support for imperfectly nested loops.
      adds  d11a9018b77 Add release notes for commit ccc4d83cda16bea1d9dfd0967dc7d2 [...]
      adds  3eecd601ed8 [OPENMP][DOCS]Update list of implemented features, NFC.
      adds  1bfcc60828d [AMDGPU] Added assert in SIFoldOperands before ptr use. NFC.
      adds  403739b2fdb [AST][NFC] Fixes a comment typo
      adds  1cce82eae84 Add more binutils tools to LLVM_INSTALL_TOOLCHAIN_ONLY target
      adds  4cbe10efc20 [AArch64] Update for Exynos
      adds  dc34b1c94df Test commit: adds a . to comment. NFC
      adds  a5c8ec4baa2 [CGDebugInfo] Emit subprograms for decls when AT_tail_call  [...]
      adds  6db7a5cd7c8 build: explicitly set the linker language for unwind
      adds  610f80f7bae [cmake] Add an option to skip stripping before install
      adds  586952f4cef Optimize std::midpoint for integers
      adds  fff2721286e [BPF] Fix CO-RE bugs with bitfields
      adds  4264e7bbfdb [CUDA][HIP] Disable emitting llvm.linker.options in device  [...]
      adds  0aba69eb1a0 [analyzer] Add test directory for scan-build.
      adds  31be9f3f7de Fix clone_constant_impl to correctly deal with null pointers
      adds  48223d92a98 [analyzer] Fixup scan-build tests for non-Darwin platforms.
      adds  abc04ff4012 [analyzer] Require darwin for scan-build tests
      adds  f65493a83e3 [X86] Teach X86MCInstLower to swap operands of commutable i [...]
      adds  9f34447f3ff [BPF] fix a use after free bug
      adds  58acbce3def [IR] Add Freeze instruction
      adds  103968d147b [X86] Lower the cost of avx512 horizontal bool and/or reduc [...]
      adds  92ef101da91 [IR] Remove switch's default block that causes clang 8 raise error
      adds  db5074dc102 [lldb][NFC] Give some parameters in CommandInterpreter more [...]
      adds  edfb8eea575 [AArch64] Update test checks on merge-store-dependency.ll. NFC
      adds  92164cf25d5 Recommit "[HardwareLoops] Optimisation remarks"
      adds  e578d0fd295 [mips] Fix `__mips_isa_rev` macros value for Octeon CPU
      adds  0d14656b9d8 [mips] Set __OCTEON__ macros
      adds  b4c5b8f3f51 DWARFDebugLoclists: Make it possible to read relocated addresses
      adds  0d47c7aba36 [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
      adds  ccf1a5f4bbe [InstCombine] dropRedundantMaskingOfLeftShiftInput(): trunc [...]
      adds  12c4a71ca9d [LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd [...]
      adds  28cf9698abd MemoryRegion: Print "don't know" permission values as such
      adds  4ecff91ed1d lldb/minidump: Add support for the alternate ARM64 constant
      adds  9a8d477a0e0 [OpenCL] Add builtin function attribute handling
      adds  0e56b0f94bf [OpenCL] Group builtin functions by prototype
      adds  9357b5d0849 Revert and patch "[Python] Remove readline module"
      adds  f71e35dc1f3 lldb/breakpad: add suppport for the "x86_64h" architecture
      adds  7d9af03ff7a [Scheduling][ARM] Consistently enable PostRA Machine scheduling
      adds  cf581d7977c [ARM] Always enable UseAA in the arm backend
      adds  646896a4422 Fix PR40644: miscompile indexed FP constant store
      adds  93767143147 [Clang FE]  Recognize -mnop-mcount CL option (SystemZ only).
      adds  2d21068d9fa [Docs] Add LangRef documentation for freeze instruction
      adds  f01b9aa89e8 [MachineScheduler] Enable AA in PostRA Machine scheduler
No new revisions were added by this update.
Summary of changes:
 clang/docs/OpenMPSupport.rst                       |   4 +-
 clang/docs/ReleaseNotes.rst                        |  48 +-
 clang/include/clang/AST/StmtOpenMP.h               |  34 +-
 clang/include/clang/Basic/CodeGenOptions.def       |   3 +
 clang/include/clang/Basic/DiagnosticCommonKinds.td |   2 +
 clang/include/clang/Basic/DiagnosticSemaKinds.td   |   6 +-
 clang/include/clang/Basic/Sanitizers.h             |   9 +-
 clang/include/clang/Driver/Options.td              |   7 +
 clang/include/clang/Lex/ModuleMap.h                |   7 +-
 clang/lib/AST/DeclCXX.cpp                          |   2 +-
 clang/lib/AST/StmtOpenMP.cpp                       |  68 +++
 clang/lib/Basic/Targets/Mips.cpp                   |   5 +-
 clang/lib/CodeGen/CGDebugInfo.cpp                  |  10 +-
 clang/lib/CodeGen/CGStmtOpenMP.cpp                 |  57 +-
 clang/lib/CodeGen/CodeGenFunction.cpp              |  14 +
 clang/lib/Driver/ToolChains/Clang.cpp              |  22 +-
 clang/lib/Driver/ToolChains/Darwin.cpp             |   4 +-
 clang/lib/Frontend/CompilerInstance.cpp            |   7 +-
 clang/lib/Frontend/CompilerInvocation.cpp          |   2 +
 clang/lib/Lex/PPMacroExpansion.cpp                 |  28 +-
 clang/lib/Sema/OpenCLBuiltins.td                   |  97 +--
 clang/lib/Sema/SemaCast.cpp                        |   2 +-
 clang/lib/Sema/SemaLookup.cpp                      |  12 +-
 clang/lib/Sema/SemaOpenMP.cpp                      |   6 +-
 clang/lib/Sema/SemaOverload.cpp                    |   5 +-
 clang/lib/Sema/TreeTransform.h                     |   2 +-
 .../multidirectory_project/directory1/file1.c      |   9 +
 .../multidirectory_project/directory2/file2.c      |   5 +
 .../scan-build/Inputs/single_null_dereference.c    |   5 +
 .../Analysis/scan-build/exclude_directories.test   |  36 ++
 clang/test/Analysis/scan-build/help.test           |  19 +
 clang/test/Analysis/scan-build/html_output.test    |  32 +
 .../Analysis/scan-build/plist_html_output.test     |  22 +
 clang/test/Analysis/scan-build/plist_output.test   |  22 +
 clang/test/CodeGen/debug-info-extern-call.c        |  21 +-
 .../CodeGen/debug-info-no-inline-line-tables.c     |  31 +
 clang/test/CodeGen/mnop-mcount.c                   |  26 +
 clang/test/CodeGenCUDA/ms-linker-options.cu        |  19 +
 .../CodeGenCXX/dbg-info-all-calls-described.cpp    |   1 +
 .../test/CodeGenOpenCL/fdeclare-opencl-builtins.cl |  22 +
 clang/test/CodeGenOpenCLCXX/addrspace-of-this.cl   |  13 +-
 clang/test/Driver/hip-autolink.hip                 |  14 +
 clang/test/Driver/x86-target-features.c            |   5 +
 clang/test/OpenMP/for_ast_print.cpp                |  34 +-
 clang/test/OpenMP/for_codegen.cpp                  |  46 ++
 clang/test/OpenMP/for_collapse_messages.cpp        |  56 +-
 clang/test/Preprocessor/init.c                     |  10 +
 clang/test/Preprocessor/microsoft-ext.c            |  13 +
 clang/test/SemaCXX/dynamic-cast.cpp                |  12 +-
 clang/test/SemaTemplate/instantiate-cast.cpp       |   2 +-
 clang/test/lit.cfg.py                              |   2 +-
 clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp | 158 ++++-
 compiler-rt/lib/asan/asan_malloc_win.cpp           |   3 -
 .../tests/sanitizer_bitvector_test.cpp             |   4 +
 libcxx/include/numeric                             |  17 +-
 libcxxabi/src/cxa_demangle.cpp                     |   8 -
 libcxxabi/src/demangle/ItaniumDemangle.h           |  74 +--
 libunwind/src/CMakeLists.txt                       |   2 +
 lld/ELF/SyntheticSections.cpp                      |   8 +-
 lld/test/ELF/arm-exidx-empty-fn.s                  |  41 ++
 lldb/cmake/modules/AddLLDB.cmake                   |  16 +-
 lldb/cmake/modules/LLDBConfig.cmake                |   1 +
 lldb/include/lldb/Interpreter/CommandInterpreter.h |   6 +-
 lldb/include/lldb/Target/MemoryRegionInfo.h        |  18 +-
 .../register/register_command/TestRegisters.py     |   1 -
 .../postmortem/minidump-new/regions-linux-map.yaml |   2 +-
 lldb/scripts/Python/python-wrapper.swig            |  20 +-
 lldb/source/Commands/CommandObjectMemory.cpp       |  13 +-
 lldb/source/Interpreter/CommandInterpreter.cpp     |  12 +-
 .../ObjectFile/Breakpad/BreakpadRecords.cpp        |   2 +-
 .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp  |  60 +-
 .../NetBSD/NativeRegisterContextNetBSD_x86_64.h    |   2 +-
 .../Process/Utility/lldb-x86-register-enums.h      |   5 +-
 .../Plugins/Process/minidump/MinidumpParser.cpp    |   1 +
 .../ScriptInterpreter/Python/CMakeLists.txt        |   1 +
 .../ScriptInterpreter/Python/PythonDataObjects.cpp |  69 +--
 .../ScriptInterpreter/Python/PythonDataObjects.h   |  18 -
 .../ScriptInterpreter/Python/PythonReadline.cpp    |  80 +++
 .../ScriptInterpreter/Python/PythonReadline.h      |  26 +
 .../Python/ScriptInterpreterPython.cpp             |  23 +-
 lldb/source/Target/MemoryRegionInfo.cpp            |  24 +-
 .../Shell/Minidump/memory-region-from-module.yaml  |   3 +-
 .../Breakpad/Inputs/line-table-edgecases.syms      |   2 +-
 .../Python/PythonDataObjectsTests.cpp              |  41 +-
 llvm/cmake/modules/AddLLVM.cmake                   |  16 +
 llvm/docs/LangRef.rst                              | 121 +++-
 llvm/docs/ReleaseNotes.rst                         |  11 +-
 llvm/include/llvm-c/Core.h                         |   2 +
 llvm/include/llvm/Analysis/AliasSetTracker.h       |   4 +-
 llvm/include/llvm/Analysis/VecFuncs.def            |  11 +-
 llvm/include/llvm/Bitcode/LLVMBitCodes.h           |   3 +-
 .../include/llvm/CodeGen/GlobalISel/IRTranslator.h |   3 +
 llvm/include/llvm/CodeGen/LivePhysRegs.h           |   3 +
 llvm/include/llvm/CodeGen/TargetSubtargetInfo.h    |   4 +
 llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h  |   9 +-
 llvm/include/llvm/Demangle/ItaniumDemangle.h       |  74 +--
 llvm/include/llvm/IR/Attributes.td                 |   1 +
 llvm/include/llvm/IR/IRBuilder.h                   |   4 +
 llvm/include/llvm/IR/Instruction.def               | 133 +++--
 llvm/include/llvm/IR/Operator.h                    |   3 +
 llvm/include/llvm/IR/PatternMatch.h                |  22 +
 llvm/include/llvm/MC/MCDwarf.h                     |   2 +-
 llvm/include/llvm/Support/TargetRegistry.h         |   2 +-
 llvm/lib/Analysis/InstructionSimplify.cpp          |  17 +-
 llvm/lib/AsmParser/LLLexer.cpp                     |   1 +
 llvm/lib/AsmParser/LLParser.cpp                    |  12 +-
 llvm/lib/AsmParser/LLToken.h                       |   1 +
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp          |  11 +-
 llvm/lib/Bitcode/Writer/BitcodeWriter.cpp          |  46 +-
 llvm/lib/CodeGen/HardwareLoops.cpp                 | 105 +++-
 llvm/lib/CodeGen/MachineScheduler.cpp              |   4 +-
 llvm/lib/CodeGen/MachineVerifier.cpp               |  26 +
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |  87 +--
 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp      |   3 +
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |  51 +-
 .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h |   1 +
 llvm/lib/CodeGen/TargetLoweringBase.cpp            |   1 +
 llvm/lib/CodeGen/TargetSubtargetInfo.cpp           |   4 +
 llvm/lib/DebugInfo/DWARF/DWARFContext.cpp          |   8 +-
 llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp         |   9 +-
 llvm/lib/DebugInfo/DWARF/DWARFDie.cpp              |  15 +-
 llvm/lib/Demangle/ItaniumDemangle.cpp              |   8 -
 llvm/lib/IR/ConstantFold.cpp                       |  65 +-
 llvm/lib/IR/Constants.cpp                          |   2 +-
 llvm/lib/IR/Core.cpp                               |   5 +
 llvm/lib/IR/Instruction.cpp                        |   1 +
 llvm/lib/IR/Instructions.cpp                       |   3 +
 llvm/lib/IR/Verifier.cpp                           |   3 +
 llvm/lib/Support/ItaniumManglingCanonicalizer.cpp  |  11 -
 llvm/lib/Support/VirtualFileSystem.cpp             |   4 +-
 llvm/lib/Target/AArch64/AArch64SchedExynosM4.td    |   6 +-
 llvm/lib/Target/AMDGPU/AMDGPUInstructions.td       |  20 +-
 llvm/lib/Target/AMDGPU/DSInstructions.td           |   2 +-
 llvm/lib/Target/AMDGPU/MIMGInstructions.td         |  10 +-
 llvm/lib/Target/AMDGPU/SIFoldOperands.cpp          |   1 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.td              |   6 +-
 llvm/lib/Target/AMDGPU/SMInstructions.td           |  10 +-
 llvm/lib/Target/AMDGPU/SOPInstructions.td          |   2 +-
 llvm/lib/Target/AMDGPU/VOP1Instructions.td         |   6 +-
 llvm/lib/Target/AMDGPU/VOP2Instructions.td         |  10 +-
 llvm/lib/Target/AMDGPU/VOP3Instructions.td         |  12 +-
 llvm/lib/Target/AMDGPU/VOP3PInstructions.td        |   4 +-
 llvm/lib/Target/AMDGPU/VOPCInstructions.td         |   2 +-
 llvm/lib/Target/ARM/ARM.td                         |  13 +-
 llvm/lib/Target/ARM/ARMCallingConv.cpp             |  44 +-
 llvm/lib/Target/ARM/ARMISelLowering.cpp            |  30 +
 llvm/lib/Target/ARM/ARMISelLowering.h              |  11 +-
 llvm/lib/Target/ARM/ARMInstrMVE.td                 |  24 +-
 llvm/lib/Target/ARM/ARMInstrNEON.td                |  16 +-
 llvm/lib/Target/ARM/ARMSubtarget.cpp               |  12 +-
 llvm/lib/Target/ARM/ARMSubtarget.h                 |   8 +-
 llvm/lib/Target/ARM/ARMTargetMachine.cpp           |  16 +-
 llvm/lib/Target/ARM/ARMTargetMachine.h             |   2 +
 llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp    |  78 +--
 llvm/lib/Target/PowerPC/CMakeLists.txt             |   1 +
 llvm/lib/Target/PowerPC/PPC.h                      |   7 +-
 llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp   | 164 +++++
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp       |   4 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp           |  55 ++
 llvm/lib/Target/RISCV/RISCVInstrInfo.h             |   8 +
 llvm/lib/Target/SystemZ/SystemZCallingConv.h       |   7 +
 llvm/lib/Target/SystemZ/SystemZCallingConv.td      |  27 +
 llvm/lib/Target/SystemZ/SystemZElimCompare.cpp     |  13 +-
 llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp   |  21 +
 llvm/lib/Target/SystemZ/SystemZISelLowering.cpp    |  18 +
 llvm/lib/Target/SystemZ/SystemZISelLowering.h      |   2 +-
 llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp    |   4 +
 llvm/lib/Target/X86/X86.td                         | 107 ++--
 .../Target/X86/X86AvoidStoreForwardingBlocks.cpp   |   8 +-
 llvm/lib/Target/X86/X86FixupLEAs.cpp               |   4 +-
 llvm/lib/Target/X86/X86FixupSetCC.cpp              |   4 +-
 llvm/lib/Target/X86/X86FlagsCopyLowering.cpp       |  16 +-
 llvm/lib/Target/X86/X86ISelLowering.cpp            |  26 +-
 llvm/lib/Target/X86/X86IndirectBranchTracking.cpp  |   4 +-
 llvm/lib/Target/X86/X86MCInstLower.cpp             |  46 ++
 llvm/lib/Target/X86/X86OptimizeLEAs.cpp            |   6 +-
 llvm/lib/Target/X86/X86RetpolineThunks.cpp         |  12 +-
 .../lib/Target/X86/X86SpeculativeLoadHardening.cpp |  12 +-
 llvm/lib/Target/X86/X86Subtarget.h                 |  10 +-
 llvm/lib/Target/X86/X86TargetTransformInfo.cpp     |  21 +
 llvm/lib/Target/X86/X86TargetTransformInfo.h       |   2 +-
 llvm/lib/Target/X86/X86VZeroUpper.cpp              |   2 +-
 llvm/lib/Target/X86/X86WinAllocaExpander.cpp       |  16 +-
 llvm/lib/Target/X86/X86WinEHState.cpp              |   2 +-
 .../Transforms/InstCombine/InstCombineShifts.cpp   |  35 +-
 llvm/lib/Transforms/Utils/InlineFunction.cpp       |  41 +-
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp          |  48 ++
 .../Vectorize/LoopVectorizationPlanner.h           |   9 +-
 llvm/lib/Transforms/Vectorize/LoopVectorize.cpp    | 203 ++++---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |  24 +-
 llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h    |  44 +-
 llvm/lib/Transforms/Vectorize/VPlan.cpp            |  23 +-
 llvm/lib/Transforms/Vectorize/VPlan.h              |  16 -
 llvm/test/Analysis/CostModel/X86/reduce-and.ll     |  42 +-
 llvm/test/Analysis/CostModel/X86/reduce-or.ll      |  42 +-
 llvm/test/Bindings/OCaml/core.ml                   |   3 +
 llvm/test/Bindings/llvm-c/echo.ll                  |   1 +
 llvm/test/Bindings/llvm-c/freeze.ll                |  22 +
 llvm/test/Bitcode/compatibility.ll                 |  14 +-
 .../test/CodeGen/AArch64/merge-store-dependency.ll |  46 +-
 llvm/test/CodeGen/ARM/O3-pipeline.ll               |   4 +
 .../CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll   |   2 +-
 llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll    |   2 +-
 .../CodeGen/ARM/cortex-a57-misched-stm-wrback.ll   |   2 +-
 llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll    |   2 +-
 .../CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll  |   2 +-
 llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll   |   2 +-
 .../CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll  |   2 +-
 llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll   |   2 +-
 llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll            |   8 +-
 llvm/test/CodeGen/ARM/postrasched.ll               |  30 +
 llvm/test/CodeGen/ARM/thumb1_return_sequence.ll    |   4 +-
 llvm/test/CodeGen/ARM/useaa.ll                     |   2 +-
 llvm/test/CodeGen/ARM/va_arg.ll                    |  51 +-
 llvm/test/CodeGen/ARM/vrev.ll                      | 243 ++++++--
 .../CodeGen/BPF/CORE/field-reloc-bitfield-1.ll     | 126 ++++
 .../CodeGen/BPF/CORE/field-reloc-bitfield-2.ll     | 124 ++++
 llvm/test/CodeGen/MSP430/shift-amount-threshold.ll |  76 +--
 llvm/test/CodeGen/PowerPC/extract-and-store.ll     |  24 +-
 llvm/test/CodeGen/PowerPC/f128-aggregates.ll       |   4 +-
 llvm/test/CodeGen/PowerPC/lower-massv-attr.ll      |  29 +
 llvm/test/CodeGen/PowerPC/lower-massv.ll           | 603 +++++++++++++++++++
 .../CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll   |  32 +-
 .../CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll   |   8 +-
 .../CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll   |  24 +-
 llvm/test/CodeGen/RISCV/disjoint.ll                |  26 +
 llvm/test/CodeGen/SystemZ/ghc-cc-01.ll             | 103 ++++
 llvm/test/CodeGen/SystemZ/ghc-cc-02.ll             |  14 +
 llvm/test/CodeGen/SystemZ/ghc-cc-03.ll             |  11 +
 llvm/test/CodeGen/SystemZ/ghc-cc-04.ll             |  16 +
 llvm/test/CodeGen/SystemZ/ghc-cc-05.ll             |  16 +
 llvm/test/CodeGen/SystemZ/ghc-cc-06.ll             |  12 +
 llvm/test/CodeGen/SystemZ/ghc-cc-07.ll             |  12 +
 .../Thumb2/LowOverheadLoops/fast-fp-loops.ll       |  13 +-
 llvm/test/CodeGen/Thumb2/mve-shufflemov.ll         | 664 +++++++++++++++++++++
 llvm/test/CodeGen/X86/avx-intel-ocl.ll             |   4 +-
 llvm/test/CodeGen/X86/avx-vzeroupper.ll            | 109 ++--
 llvm/test/CodeGen/X86/avx512-mask-op.ll            |  52 +-
 llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll     |  16 +-
 llvm/test/CodeGen/X86/avx512-vselect.ll            |   2 +-
 llvm/test/CodeGen/X86/known-signbits-vector.ll     | 319 +++++-----
 llvm/test/CodeGen/X86/madd.ll                      |   4 +-
 llvm/test/CodeGen/X86/masked_compressstore.ll      |  22 +-
 llvm/test/CodeGen/X86/masked_expandload.ll         |  22 +-
 llvm/test/CodeGen/X86/midpoint-int-vec-256.ll      |  60 +-
 llvm/test/CodeGen/X86/pr29112.ll                   |   4 +-
 llvm/test/CodeGen/X86/sad.ll                       |  18 +-
 llvm/test/CodeGen/X86/uadd_sat_vec.ll              |   4 +-
 llvm/test/CodeGen/X86/vec_umulo.ll                 |  24 +-
 llvm/test/CodeGen/X86/vector-fshl-256.ll           |  18 +-
 llvm/test/CodeGen/X86/vector-fshl-512.ll           |  44 +-
 llvm/test/CodeGen/X86/vector-fshl-rot-256.ll       |   8 +-
 llvm/test/CodeGen/X86/vector-fshl-rot-512.ll       |  18 +-
 llvm/test/CodeGen/X86/vector-fshr-256.ll           |  20 +-
 llvm/test/CodeGen/X86/vector-fshr-512.ll           |  34 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-256.ll       |   8 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-512.ll       |  24 +-
 llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll      |   4 +-
 llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll      |   4 +-
 llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll      |   4 +-
 llvm/test/CodeGen/X86/vector-rotate-256.ll         |   8 +-
 llvm/test/CodeGen/X86/vector-rotate-512.ll         |  14 +-
 .../CodeGen/X86/vector-shift-by-select-loop.ll     |   8 +-
 llvm/test/CodeGen/X86/vector-trunc-math.ll         |   8 +-
 llvm/test/CodeGen/X86/vector-trunc-packus.ll       |   4 +-
 llvm/test/CodeGen/X86/x86-interleaved-access.ll    |   6 +-
 .../DebugInfo/X86/dwarf-callsite-related-attrs.ll  |   9 +
 llvm/test/MachineVerifier/live-ins-01.mir          |  57 ++
 llvm/test/MachineVerifier/live-ins-02.mir          |  32 +
 llvm/test/MachineVerifier/live-ins-03.mir          |  36 ++
 .../test/Transforms/HardwareLoops/ARM/structure.ll |  25 +-
 .../Transforms/Inline/no-inline-line-tables.ll     |  99 +++
 ...ift-input-masking-after-truncation-variant-a.ll |  24 +-
 ...ift-input-masking-after-truncation-variant-b.ll |  24 +-
 ...ift-input-masking-after-truncation-variant-c.ll |  24 +-
 ...ift-input-masking-after-truncation-variant-d.ll |  24 +-
 ...ift-input-masking-after-truncation-variant-e.ll |  24 +-
 ...ift-input-masking-after-truncation-variant-a.ll |  16 +-
 ...ift-input-masking-after-truncation-variant-b.ll |  16 +-
 ...ift-input-masking-after-truncation-variant-c.ll |  16 +-
 ...ift-input-masking-after-truncation-variant-d.ll |  16 +-
 ...ift-input-masking-after-truncation-variant-e.ll |  16 +-
 ...ift-input-masking-after-truncation-variant-f.ll |  16 +-
 llvm/test/Transforms/InstSimplify/fcmp-select.ll   | 168 ++++++
 .../Transforms/LoopUnroll/peel-loop-conditions.ll  |  98 +++
 llvm/test/Transforms/MergeFunc/inline-asm.ll       |   6 +-
 .../test/Transforms/SLPVectorizer/X86/crash_gep.ll |  23 +
 llvm/test/Transforms/SimplifyCFG/wc-widen-block.ll | 316 ++++++++++
 llvm/test/tools/llvm-ar/mri-nonascii.test          |  21 +
 llvm/test/tools/llvm-ar/mri-utf8.test              |  23 -
 .../test/tools/llvm-dwarfdump/X86/debug_loclists.s | 120 ++++
 llvm/tools/llvm-c-test/echo.cpp                    |  12 +
 llvm/unittests/Transforms/Vectorize/VPlanTest.cpp  |   1 -
 .../llvm/lib/Target/AArch64/AsmParser/BUILD.gn     |   5 +-
 .../gn/secondary/llvm/lib/Target/AArch64/BUILD.gn  |  10 +-
 .../gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn  |   1 +
 .../llvm/lib/Target/RISCV/AsmParser/BUILD.gn       |   5 +-
 .../gn/secondary/llvm/lib/Target/RISCV/BUILD.gn    |   3 +
 .../secondary/llvm/lib/Transforms/Scalar/BUILD.gn  |   2 +-
 .../llvm/unittests/Transforms/Utils/BUILD.gn       |   2 +-
 llvm/utils/lit/lit/cl_arguments.py                 |   1 +
 llvm/utils/lit/lit/llvm/config.py                  |   1 +
 llvm/utils/lit/lit/main.py                         |  23 +-
 llvm/utils/lit/lit/run.py                          |  13 +-
 llvm/utils/lit/tests/selecting.py                  |  19 +-
 openmp/libomptarget/plugins/cuda/src/rtl.cpp       |   2 +-
 306 files changed, 6717 insertions(+), 2041 deletions(-)
 create mode 100644 clang/test/Analysis/scan-build/Inputs/multidirectory_project/di [...]
 create mode 100644 clang/test/Analysis/scan-build/Inputs/multidirectory_project/di [...]
 create mode 100644 clang/test/Analysis/scan-build/Inputs/single_null_dereference.c
 create mode 100644 clang/test/Analysis/scan-build/exclude_directories.test
 create mode 100644 clang/test/Analysis/scan-build/help.test
 create mode 100644 clang/test/Analysis/scan-build/html_output.test
 create mode 100644 clang/test/Analysis/scan-build/plist_html_output.test
 create mode 100644 clang/test/Analysis/scan-build/plist_output.test
 create mode 100644 clang/test/CodeGen/debug-info-no-inline-line-tables.c
 create mode 100644 clang/test/CodeGen/mnop-mcount.c
 create mode 100644 clang/test/CodeGenCUDA/ms-linker-options.cu
 create mode 100644 clang/test/CodeGenOpenCL/fdeclare-opencl-builtins.cl
 create mode 100644 clang/test/Driver/hip-autolink.hip
 create mode 100644 lld/test/ELF/arm-exidx-empty-fn.s
 create mode 100644 lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp
 create mode 100644 lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h
 create mode 100644 llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp
 create mode 100644 llvm/test/Bindings/llvm-c/freeze.ll
 create mode 100644 llvm/test/CodeGen/ARM/postrasched.ll
 create mode 100644 llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
 create mode 100644 llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/lower-massv-attr.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/lower-massv.ll
 create mode 100644 llvm/test/CodeGen/RISCV/disjoint.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-01.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-02.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-03.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-04.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-05.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-06.ll
 create mode 100644 llvm/test/CodeGen/SystemZ/ghc-cc-07.ll
 create mode 100644 llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
 create mode 100644 llvm/test/MachineVerifier/live-ins-01.mir
 create mode 100644 llvm/test/MachineVerifier/live-ins-02.mir
 create mode 100644 llvm/test/MachineVerifier/live-ins-03.mir
 create mode 100644 llvm/test/Transforms/Inline/no-inline-line-tables.ll
 create mode 100644 llvm/test/Transforms/SimplifyCFG/wc-widen-block.ll
 create mode 100644 llvm/test/tools/llvm-ar/mri-nonascii.test
 delete mode 100644 llvm/test/tools/llvm-ar/mri-utf8.test
 create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_loclists.s
-- 
To stop receiving notification emails like this one, please contact
the administrator of this repository.

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig updated (ef85f47595a -> f01b9aa89e8)