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from e00eaf45f72 [JITLink] Fix bogus TimerGroup constructor call. new 2251d7e2609 AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization new 22857d804d4 [Tblgen][MCA] Add the ability to mark groups as LoadQueue a [...] new d2c4dd208de [ORCv2] - New Speculate Query Implementation
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Summary of changes: examples/SpeculativeJIT/SpeculativeJIT.cpp | 5 +- .../llvm/ExecutionEngine/Orc/SpeculateAnalyses.h | 55 ++++- include/llvm/ExecutionEngine/Orc/Speculation.h | 57 +++--- include/llvm/Target/TargetSchedule.td | 8 +- lib/ExecutionEngine/Orc/SpeculateAnalyses.cpp | 222 +++++++++++++++++++-- lib/ExecutionEngine/Orc/Speculation.cpp | 135 +++++++++---- lib/MCA/HardwareUnits/LSUnit.cpp | 4 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 + lib/Target/AMDGPU/SIMachineFunctionInfo.h | 5 +- .../MIR/AMDGPU/machine-function-info-no-ir.mir | 4 + test/CodeGen/MIR/AMDGPU/machine-function-info.ll | 13 +- 11 files changed, 411 insertions(+), 99 deletions(-)