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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project.
from fe1b8a09113 [NativePDB] Make GetOrCreateDeclForUid return an lldb CompilerDecl adds 8a431874e99 [NFC][InstCombine] Add a few extra srem-by-power-of-two tes [...] adds ca9dfdfaeca [lldb] Fix crash when looking up type coming from the Clang [...] adds c38899fc26e [ARM] Move MVE VPT block tests into the Thumb2 directory. NFC adds d7504a1569d [GISel]: Attach missing range metadata while translating G_LOADs adds 630be14ac64 [SmallBitVector] Fix bug in find_next_unset for small types [...] adds e6cd20ba534 [InstCombine] Update comment I missed in r366649. NFC adds 73d641a23c2 [PowerPC][NFC] Regenerate test using script adds 86fa3270ef6 [X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_B [...] adds 3d68adebc57 [PowerPC][NFC] Precomit test case for upcoming patch adds ee5dc7e7ad8 [InstCombine] Add foldAndOfICmps test cases inspired by PR42691. adds 1a1af4392ac [analyzer] Fix -Wunused-function in NDEBUG builds with #ifd [...] adds 6ef23e65818 [utils] Clean up UpdateTestChecks/common.py adds c6c31da8677 [Loop Peeling] Fix the handling of branch weights of peeled [...] adds 3d72a58981e [PowerPC][NFC] Precommit a test case where ppc-mi-peepholes [...] adds 298500ae331 [AMDGPU] Save some work when an atomic op has no uses
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Summary of changes: clang/lib/StaticAnalyzer/Core/RegionStore.cpp | 6 +- .../test/lang/objc/modules/TestObjCModules.py | 4 + .../Clang/ClangModulesDeclVendor.cpp | 12 +- llvm/include/llvm/ADT/SmallBitVector.h | 2 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +- llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp | 137 +++++++-------- llvm/lib/Target/X86/X86ISelLowering.cpp | 32 ++-- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 2 +- llvm/lib/Transforms/Utils/LoopUnrollPeel.cpp | 103 +++++------ .../AArch64/GlobalISel/arm64-irtranslator.ll | 11 +- .../MIR/PowerPC/peephole-miscompile-extswsli.mir | 66 +++++++ llvm/test/CodeGen/PowerPC/dform-adjust.ll | 125 ++++++++++++++ llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 189 ++++++++++++++++++--- .../test/CodeGen/{ARM => Thumb2}/mve-vpt-block.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block2.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block3.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block4.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block5.mir | 0 .../CodeGen/{ARM => Thumb2}/mve-vpt-block6.mir | 0 llvm/test/Transforms/InstCombine/and-or-icmps.ll | 39 +++++ llvm/test/Transforms/InstCombine/rem.ll | 37 ++++ .../Transforms/LoopUnroll/peel-loop-pgo-deopt.ll | 16 +- llvm/test/Transforms/LoopUnroll/peel-loop-pgo.ll | 8 +- llvm/unittests/ADT/BitVectorTest.cpp | 32 ++++ llvm/utils/UpdateTestChecks/common.py | 12 +- 25 files changed, 639 insertions(+), 199 deletions(-) create mode 100644 llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir create mode 100644 llvm/test/CodeGen/PowerPC/dform-adjust.ll rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block2.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block3.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block4.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block5.mir (100%) rename llvm/test/CodeGen/{ARM => Thumb2}/mve-vpt-block6.mir (100%)