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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/qemu.
from 212a33d3b0 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu [...] adds 915f77b211 target/riscv: zfh: half-precision load and store adds 00c1899f12 target/riscv: zfh: half-precision computational adds 7b03c8e5b5 target/riscv: zfh: half-precision convert and move adds 11f9c450a6 target/riscv: zfh: half-precision floating-point compare adds 6bc6fc96d1 target/riscv: zfh: half-precision floating-point classify adds 13fb8c7b42 target/riscv: zfh: add Zfh cpu property adds 2d258b428b target/riscv: zfh: implement zfhmin extension adds e523773040 target/riscv: zfh: add Zfhmin cpu property adds 9ec6622db3 target/riscv: drop vector 0.7.1 and add 1.0 support adds 52561f2a80 target/riscv: Use FIELD_EX32() to extract wd field adds 61b4b69d12 target/riscv: rvv-1.0: add mstatus VS field adds c36b2f1a4d target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty adds 89a81e376a target/riscv: rvv-1.0: add sstatus VS field adds 7b07a37c2c target/riscv: rvv-1.0: introduce writable misa.v field adds 8e1ee1fb57 target/riscv: rvv-1.0: add translation-time vector context status adds 9bd291f6e3 target/riscv: rvv-1.0: remove rvv related codes from fcsr registers adds 4594fa5a96 target/riscv: rvv-1.0: add vcsr register adds 2e56505475 target/riscv: rvv-1.0: add vlenb register adds 6bc3dfa96d target/riscv: rvv-1.0: check MSTATUS_VS when accessing vecto [...] adds f9298de514 target/riscv: rvv-1.0: remove MLEN calculations adds 33f1beaf12 target/riscv: rvv-1.0: add fractional LMUL adds 3479a814e4 target/riscv: rvv-1.0: add VMA and VTA adds f31dacd720 target/riscv: rvv-1.0: update check functions adds ff64fc91d1 target/riscv: introduce more imm value modes in translator f [...] adds 9b4a40a786 target/riscv: rvv:1.0: add translation-time nan-box helper function adds 57a2d89a82 target/riscv: rvv-1.0: remove amo operations instructions adds d9b7609a1f target/riscv: rvv-1.0: configure instructions adds 79556fb6fa target/riscv: rvv-1.0: stride load and store instructions adds 08b9d0ed4a target/riscv: rvv-1.0: index load and store instructions adds 83fcd573b1 target/riscv: rvv-1.0: fix address index overflow bug of ind [...] adds d3e5e2ff4f target/riscv: rvv-1.0: fault-only-first unit stride load adds 30206bd842 target/riscv: rvv-1.0: load/store whole register instructions adds 5a9f8e1552 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns adds a689a82b7f target/riscv: rvv-1.0: take fractional LMUL into vector max [...] adds 20f2079acf target/riscv: rvv-1.0: floating-point square-root instruction adds 0676d8e3dc target/riscv: rvv-1.0: floating-point classify instructions adds 0014aa741d target/riscv: rvv-1.0: count population in mask instruction adds d71a24fc82 target/riscv: rvv-1.0: find-first-set mask bit instruction adds 40c1495d69 target/riscv: rvv-1.0: set-X-first mask bit instructions adds ee17eaa120 target/riscv: rvv-1.0: iota instruction adds f4f47e04de target/riscv: rvv-1.0: element index instruction adds 308ee80578 target/riscv: rvv-1.0: allow load element with sign-extended adds 50bfb45b2c target/riscv: rvv-1.0: register gather instructions adds dedc53cbc9 target/riscv: rvv-1.0: integer scalar move instructions adds c4b3e46f00 target/riscv: rvv-1.0: floating-point move instruction adds 5c4eb8fb56 target/riscv: rvv-1.0: floating-point scalar move instructions adds 6b85975e11 target/riscv: rvv-1.0: whole register move instructions adds cd01340e75 target/riscv: rvv-1.0: integer extension instructions adds 8b99a110f7 target/riscv: rvv-1.0: single-width averaging add and subtra [...] adds a75ae09f2a target/riscv: rvv-1.0: single-width bit shift instructions adds bb45485ad1 target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow adds 7daa5852bc target/riscv: rvv-1.0: narrowing integer right shift instructions adds f51c3cf1fa target/riscv: rvv-1.0: widening integer multiply-add instructions adds d6be7a3504 target/riscv: rvv-1.0: single-width saturating add and subtr [...] adds 063f8bbca0 target/riscv: rvv-1.0: integer comparison instructions adds e70aa16e5e target/riscv: rvv-1.0: floating-point compare instructions adds 50f6696c0f target/riscv: rvv-1.0: mask-register logical instructions adds 6438ed61de target/riscv: rvv-1.0: slide instructions adds 8500d4ab2e target/riscv: rvv-1.0: floating-point slide instructions adds a70b3a73e7 target/riscv: rvv-1.0: narrowing fixed-point clip instructions adds 08b60eebc4 target/riscv: rvv-1.0: single-width floating-point reduction adds b8dd99f2d1 target/riscv: rvv-1.0: widening floating-point reduction ins [...] adds 74eb7834bc target/riscv: rvv-1.0: single-width scaling shift instructions adds a12c812d19 target/riscv: rvv-1.0: remove widening saturating scaled mul [...] adds e29c5cefd8 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf adds c3536f2f55 target/riscv: rvv-1.0: remove integer extract instruction adds 49c5611a97 target/riscv: rvv-1.0: floating-point min/max instructions adds 986c895de1 target/riscv: introduce floating-point rounding mode enum adds 900da87ab9 target/riscv: rvv-1.0: floating-point/integer type-convert i [...] adds 3ce4c09df7 target/riscv: rvv-1.0: widening floating-point/integer type-convert adds 75804f7131 target/riscv: add "set round to odd" rounding mode helper function adds ff679b58e3 target/riscv: rvv-1.0: narrowing floating-point/integer type [...] adds 8a4b52575a target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits adds f714361ed7 target/riscv: rvv-1.0: implement vstart CSR adds d6c4d3f2a6 target/riscv: rvv-1.0: trigger illegal instruction exception [...] adds 719d3561b2 target/riscv: gdb: support vector registers for rv64 & rv32 adds e848a1e563 target/riscv: rvv-1.0: floating-point reciprocal square-root [...] adds 55c35407c3 target/riscv: rvv-1.0: floating-point reciprocal estimate in [...] adds 6b5c8eb3e7 target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 adds 34a2c2d81a target/riscv: rvv-1.0: add vsetivli instruction adds 5c89e9c096 target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() adds 26086aea0d target/riscv: rvv-1.0: add vector unit-stride mask load/store insns adds 9c0d2559de target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to [...] adds 45ca2ca6bd target/riscv: rvv-1.0: update opivv_vadc_check() comment adds cc13aa3614 target/riscv: rvv-1.0: Add ELEN checks for widening and narr [...] adds a7cad953fa riscv: Set 5.4 as minimum kernel version for riscv32 adds 0643c12e4b target/riscv: Enable bitmanip Zb[abcs] instructions adds 7e322a7f23 hw/riscv: Use load address rather than entry point for fw_dy [...] adds c7d773ae49 Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:ali [...]
No new revisions were added by this update.
Summary of changes: hw/riscv/boot.c | 13 +- linux-user/riscv/target_syscall.h | 3 +- target/riscv/cpu.c | 28 +- target/riscv/cpu.h | 63 +- target/riscv/cpu_bits.h | 10 + target/riscv/cpu_helper.c | 39 +- target/riscv/csr.c | 63 +- target/riscv/fpu_helper.c | 197 +- target/riscv/gdbstub.c | 184 ++ target/riscv/helper.h | 464 ++-- target/riscv/insn32.decode | 332 +-- target/riscv/insn_trans/trans_rvv.c.inc | 2429 ++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 537 +++++ target/riscv/internals.h | 40 +- target/riscv/translate.c | 93 +- target/riscv/vector_helper.c | 3601 +++++++++++++++-------------- 16 files changed, 4997 insertions(+), 3099 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc