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from 139bd3198a7 RISC-V: Add the mini support for SiFive extensions. new c10767d0e49 RISC-V: Fix incorrect optimization options passing to strid [...] new 7c7da103650 RISC-V: Refine the rtl expand check for strided ld/st
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Summary of changes: .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +- 12 files changed, 56 insertions(+), 34 deletions(-)