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from 7d554943ba2 sim: mips/or1k: drop redundant arg to bitsize macro new 23ff54c27d5 RISC-V: Support svinval extension with frozen version 1.0.
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Summary of changes: bfd/elfxx-riscv.c | 3 +++ gas/testsuite/gas/riscv/svinval.d | 15 +++++++++++++++ gas/testsuite/gas/riscv/svinval.s | 5 +++++ include/opcode/riscv-opc.h | 16 ++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 7 +++++++ 6 files changed, 47 insertions(+) create mode 100644 gas/testsuite/gas/riscv/svinval.d create mode 100644 gas/testsuite/gas/riscv/svinval.s