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from 868fc62791b RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU [...] new 940d5b56990 riscv: improve cost model for loading 64bit constant in rv32
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Summary of changes: gcc/config/riscv/riscv.cc | 24 +++++++++++++ .../gcc.target/riscv/rv32-load-64bit-constant.c | 40 ++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rv32-load-64bit-constant.c