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from 6c1da931e78 AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD new 47f39c041e0 [NFC][InstCombine][InstSimplify] PR43251 - and some pattern [...] new 2ee28d2387e AMDGPU/GlobalISel: Select llvm.amdgcn.sffbh new b4ba7acc496 AMDGPU/GlobalISel: Select cvt pk intrinsics new cae6fe6cdbc AMDGPU/GlobalISel: Select G_FABS/G_FNEG
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Summary of changes: lib/Target/AMDGPU/AMDGPUGISel.td | 9 - lib/Target/AMDGPU/AMDGPUInstrInfo.td | 36 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 14 +- lib/Target/AMDGPU/SIInstructions.td | 130 ++++-- lib/Target/AMDGPU/VOP1Instructions.td | 2 +- .../GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir | 67 +++ .../GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir | 67 +++ .../inst-select-amdgcn.cvt.pknorm.i16.mir | 67 +++ .../inst-select-amdgcn.cvt.pknorm.u16.mir | 67 +++ .../GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir | 80 ++-- .../AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir | 62 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 247 ++++++++++ .../GlobalISel/inst-select-fcanonicalize.mir | 18 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 513 +++++++++++++++++++++ test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 158 ++----- test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 158 ++----- test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 146 +++--- test/CodeGen/AMDGPU/fneg-combines.ll | 6 +- test/CodeGen/AMDGPU/fneg.ll | 17 +- .../result-of-usub-is-non-zero-and-no-overflow.ll | 58 ++- ...-usub-by-nonzero-is-non-zero-and-no-overflow.ll | 84 ++++ 21 files changed, 1593 insertions(+), 413 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir create mode 100644 test/Transforms/InstSimplify/result-of-usub-by-nonzero-is-non-z [...]