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from 328e67adb1e [PowerPC][Power9]Legalize and emit code for quad-precision [...] new 10888ceb0ed [X86] Correct the SchedRW on (V)MOVAPSrr_REV and similar to [...] new 369474116d7 [X86] Correct regular expression in Zen scheduler model tha [...] new e7f0446eb91 [X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skyla [...] new 0dec787211a [X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge [...] new 3c8e8f0115a [X86] Add JMP16r and JMP32r to Sandybridge scheduler model. new 2518feb69d6 [Hexagon] Add a few more lit tests
The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: lib/Target/X86/X86InstrSSE.td | 4 +- lib/Target/X86/X86SchedBroadwell.td | 2 +- lib/Target/X86/X86SchedHaswell.td | 2 +- lib/Target/X86/X86SchedSandyBridge.td | 8 +- lib/Target/X86/X86SchedSkylakeClient.td | 2 +- lib/Target/X86/X86SchedSkylakeServer.td | 2 +- lib/Target/X86/X86ScheduleZnver1.td | 2 +- test/CodeGen/Hexagon/S3_2op.ll | 364 +++++++++++++++++++++ test/CodeGen/Hexagon/fp_latency.ll | 88 +++++ test/CodeGen/Hexagon/mem-ops-sub_01.ll | 44 +++ .../{mem-ops-sub_i16_01.ll => mem-ops-sub_i16.ll} | 8 +- test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll | 2 +- test/CodeGen/Hexagon/postinc-order.ll | 68 ++++ test/CodeGen/Hexagon/swp-change-dep1.ll | 43 +++ test/CodeGen/Hexagon/swp-conv3x3-nested.ll | 185 +++++++++++ test/CodeGen/Hexagon/swp-dep-neg-offset.ll | 67 ++++ test/CodeGen/Hexagon/swp-epilog-phi2.ll | 65 ++++ test/CodeGen/Hexagon/swp-listen-loop3.ll | 69 ++++ test/CodeGen/Hexagon/swp-max-stage3.ll | 50 +++ test/CodeGen/Hexagon/swp-reuse-phi-6.ll | 106 ++++++ test/CodeGen/Hexagon/swp-sigma.ll | 203 ++++++++++++ test/CodeGen/Hexagon/tfr-cleanup.ll | 83 +++++ test/CodeGen/Hexagon/v6vec-vmemu1.ll | 67 ++++ test/CodeGen/Hexagon/v6vec-vmemu2.ll | 32 ++ test/CodeGen/Hexagon/v6vec_inc1.ll | 73 +++++ test/CodeGen/X86/schedule-x86_32.ll | 22 +- test/CodeGen/X86/schedule-x86_64.ll | 30 +- 27 files changed, 1647 insertions(+), 44 deletions(-) create mode 100644 test/CodeGen/Hexagon/S3_2op.ll create mode 100644 test/CodeGen/Hexagon/fp_latency.ll create mode 100644 test/CodeGen/Hexagon/mem-ops-sub_01.ll copy test/CodeGen/Hexagon/{mem-ops-sub_i16_01.ll => mem-ops-sub_i16.ll} (84%) create mode 100644 test/CodeGen/Hexagon/postinc-order.ll create mode 100644 test/CodeGen/Hexagon/swp-change-dep1.ll create mode 100644 test/CodeGen/Hexagon/swp-conv3x3-nested.ll create mode 100644 test/CodeGen/Hexagon/swp-dep-neg-offset.ll create mode 100644 test/CodeGen/Hexagon/swp-epilog-phi2.ll create mode 100644 test/CodeGen/Hexagon/swp-listen-loop3.ll create mode 100644 test/CodeGen/Hexagon/swp-max-stage3.ll create mode 100644 test/CodeGen/Hexagon/swp-reuse-phi-6.ll create mode 100644 test/CodeGen/Hexagon/swp-sigma.ll create mode 100644 test/CodeGen/Hexagon/tfr-cleanup.ll create mode 100644 test/CodeGen/Hexagon/v6vec-vmemu1.ll create mode 100644 test/CodeGen/Hexagon/v6vec-vmemu2.ll create mode 100644 test/CodeGen/Hexagon/v6vec_inc1.ll