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from 9fde76a3be8 RISC-V: Fix riscv/arch-19.c with different ISA spec version new 7b206ae7f17 RISC-V: Fix RVV register order
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Summary of changes: gcc/config/riscv/riscv.h | 13 ++++----- .../gcc.target/riscv/rvv/base/reg_order-1.c | 20 ++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-4.c | 32 +++++++++++----------- gcc/testsuite/gcc.target/riscv/rvv/base/spill-6.c | 16 +++++------ 4 files changed, 50 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/reg_order-1.c