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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-arm-build_cross in repository toolchain/ci/qemu.
from f4ef8c9cc1 Merge remote-tracking branch 'remotes/ehabkost/tags/machine- [...] new 5e4b6bb1e8 hw/mips/fuloong2e: Convert pointless error message to an assert() new 0c66619835 hw/isa/isa-bus: Replace hw_error() by assert() new 8ff362df0f hw/acpi/tco: Remove unused definitions new dfd4981a68 hw/gpio/omap_gpio: Replace fprintf() by qemu_log_mask(GUEST_ERROR) new 1c3bd33a5e hw/gpio/max7310: Replace disabled printf() by qemu_log_mask(UNIMP) new 8dc746b2ae Makefile: Drop extra phony cscope new c857f9050c Makefile: Skip the meson subdir in cscope/TAGS/ctags new 4a4a604cc6 hw/net/e1000e: Remove overwritten read handler for STATUS register new fb1953b22a hw/net/e1000e: Remove duplicated write handler for FLSWDATA [...] new a8dc2aceab meson.build: tweak sdl-image error message new 231073f7fb kconfig: fix comment referring to old Makefiles new 8b39aa90e9 hw: hyperv: vmbus: Fix 32bit compilation new 712f197436 test-vmstate: remove unnecessary code in match_interval_mapp [...] new b199c682f1 target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() new 5ace4cc0e8 hw/arm/pxa2xx: Add missing fallthrough comment new 67263b33af util/hexdump: Convert to take a void pointer argument new b42581f5bb util/hexdump: Reorder qemu_hexdump() arguments new 8821e21414 target/i386/kvm: Add missing fallthrough comment new 842038f55c Merge remote-tracking branch 'remotes/vivier2/tags/trivial-b [...] new ca04c3cf15 tests: fix output message formatting for crypto benchmarks new eba29771c0 crypto: Assume blocksize is a power of 2 new 6d92bdf443 crypto: Rename cipher include files to .c.inc new 7d823bf4e9 crypto: Remove redundant includes new d6f77401be crypto/nettle: Fix xts_encrypt arguments new 954721ffa8 crypto: Move QCryptoCipherDriver typedef to crypto/cipher.h new 7b5dbfb777 crypto: Use the correct const type for driver new 3eedf5cc9d crypto: Allocate QCryptoCipher with the subclass new da30cd77e1 crypto: Move cipher->driver init to qcrypto_*_cipher_ctx_new new e46064a4c6 crypto: Constify cipher data tables new 838e4631cb crypto/builtin: Remove odd-sized AES block handling new 8ee47cddbe crypto/builtin: Merge qcrypto_cipher_aes_{ecb,xts}_{en,de}crypt new a2d76b6b2e crypto/builtin: Move AES_cbc_encrypt into cipher-builtin.inc.c new ef186f4bc2 crypto/builtin: Split and simplify AES_encrypt_cbc new a3db31b83e crypto/builtin: Split QCryptoCipherBuiltin into subclasses new 53ddad9b83 crypto/nettle: Split QCryptoCipherNettle into subclasses new 1b010d9339 crypto/gcrypt: Split QCryptoCipherGcrypt into subclasses new c47edb8dda Merge remote-tracking branch 'remotes/berrange-gitlab/tags/c [...] new bc3bde8448 CODING_STYLE.rst: flesh out our naming conventions. new 4969e697c1 usb-host: restrict workaround to new libusb versions new 7f80868744 tests/meson.build: fp tests don't need CONFIG_TCG new 102661430c target/mips: simplify gen_compute_imm_branch logic new c609274b85 docs/system/deprecated: mark ppc64abi32-linux-user for deprecation new 2d838d9bae configure: don't enable ppc64abi32-linux-user by default new c768eef18c hw/i386: make explicit clearing of pch_rev_id new 94b4ec24b9 tests: bump avocado version new 89e076f37d tests/acceptance: Add Test.fetch_asset(cancel_on_missing=True) new c17a386b6a plugins: move the more involved plugins to contrib new 3d9f371b01 Merge remote-tracking branch 'remotes/stsquad/tags/pull-test [...] new c51a3f5d15 target/riscv: Fix bug in getting trap cause name for trace_r [...] new ab3d207fe8 riscv: sifive_test: Allow 16-bit writes to memory region new 9b4c9b2b2a target/riscv: cpu: Add a new 'resetvec' property new 4100d5e6dc hw/riscv: hart: Add a new 'resetvec' property new 73f6ed97ac target/riscv: cpu: Set reset vector based on the configured [...] new 56f6e31e7b hw/riscv: Initial support for Microchip PolarFire SoC Icicle [...] new a8fb0a500a hw/char: Add Microchip PolarFire SoC MMUART emulation new 8f2ac39d5d hw/riscv: microchip_pfsoc: Connect 5 MMUARTs new c696e1f2b3 hw/sd: Add Cadence SDHCI emulation new 898dc008e8 hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controlle [...] new 97ba42230b hw/dma: Add SiFive platform DMA controller emulation new 7124e27bb8 hw/riscv: microchip_pfsoc: Connect a DMA controller new 64ac13633f hw/net: cadence_gem: Add a new 'phy-addr' property new dfc388797c hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 new 47374b0761 hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs new ce908a2f6f hw/riscv: microchip_pfsoc: Hook GPIO controllers new a47ef6e93a hw/riscv: clint: Avoid using hard-coded timebase frequency new 834e027a34 hw/riscv: sifive_u: Connect a DMA controller new 89ece6f76f hw/riscv: Move sifive_e_prci model to hw/misc new 9fe640a53d hw/riscv: Move sifive_u_prci model to hw/misc new 0fa9e32945 hw/riscv: Move sifive_u_otp model to hw/misc new 4921a0ce86 hw/riscv: Move sifive_gpio model to hw/gpio new 406fafd5d0 hw/riscv: Move sifive_clint model to hw/intc new 84fcf3c151 hw/riscv: Move sifive_plic model to hw/intc new 70eb9f9cd1 hw/riscv: Move riscv_htif model to hw/char new b609b7e319 hw/riscv: Move sifive_uart model to hw/char new a4b84608ba hw/riscv: Move sifive_test model to hw/misc new 30a4af1664 hw/riscv: Always build riscv_hart.c new 4791b4c4ab hw/riscv: Drop CONFIG_SIFIVE new 7595a65818 hw/riscv: Sort the Kconfig options in alphabetical order new f00f57f344 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...]
The 79 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: .travis.yml | 2 +- CODING_STYLE.rst | 37 +- Kconfig.host | 4 +- MAINTAINERS | 12 +- Makefile | 21 +- configure | 48 +- contrib/plugins/Makefile | 42 ++ {tests/plugin => contrib/plugins}/hotblocks.c | 0 {tests/plugin => contrib/plugins}/hotpages.c | 0 {tests/plugin => contrib/plugins}/howvec.c | 0 {tests/plugin => contrib/plugins}/lockstep.c | 0 crypto/aes.c | 51 -- crypto/afalgpriv.h | 3 + crypto/cipher-afalg.c | 25 +- crypto/cipher-builtin.c | 532 ----------------- crypto/cipher-builtin.c.inc | 435 ++++++++++++++ crypto/{cipher-gcrypt.c => cipher-gcrypt.c.inc} | 503 ++++++++-------- crypto/cipher-nettle.c | 733 ----------------------- crypto/cipher-nettle.c.inc | 760 ++++++++++++++++++++++++ crypto/cipher.c | 44 +- crypto/cipherpriv.h | 6 +- default-configs/riscv64-softmmu.mak | 1 + docs/devel/tcg-plugins.rst | 146 +++++ docs/system/deprecated.rst | 7 + hw/acpi/tco.c | 11 - hw/arm/pxa2xx.c | 2 +- hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 2 + hw/char/Kconfig | 9 + hw/char/mchp_pfsoc_mmuart.c | 86 +++ hw/char/meson.build | 3 + hw/{riscv => char}/riscv_htif.c | 2 +- hw/{riscv => char}/sifive_uart.c | 2 +- hw/dma/Kconfig | 3 + hw/dma/meson.build | 1 + hw/dma/sifive_pdma.c | 313 ++++++++++ hw/dma/xlnx_dpdma.c | 2 +- hw/gpio/Kconfig | 3 + hw/gpio/max7310.c | 11 +- hw/gpio/meson.build | 1 + hw/gpio/omap_gpio.c | 6 +- hw/{riscv => gpio}/sifive_gpio.c | 2 +- hw/gpio/trace-events | 6 + hw/hyperv/vmbus.c | 3 +- hw/i386/pc_piix.c | 2 +- hw/intc/Kconfig | 6 + hw/intc/meson.build | 2 + hw/{riscv => intc}/sifive_clint.c | 28 +- hw/{riscv => intc}/sifive_plic.c | 2 +- {include/hw/riscv => hw/intc}/sifive_plic.h | 0 hw/isa/isa-bus.c | 9 +- hw/mips/fuloong2e.c | 5 +- hw/misc/Kconfig | 12 + hw/misc/meson.build | 6 + hw/{riscv => misc}/sifive_e_prci.c | 2 +- hw/{riscv => misc}/sifive_test.c | 4 +- hw/{riscv => misc}/sifive_u_otp.c | 2 +- hw/{riscv => misc}/sifive_u_prci.c | 2 +- hw/net/cadence_gem.c | 7 +- hw/net/e1000e_core.c | 2 - hw/net/fsl_etsec/etsec.c | 2 +- hw/net/fsl_etsec/rings.c | 2 +- hw/riscv/Kconfig | 70 ++- hw/riscv/meson.build | 12 +- hw/riscv/microchip_pfsoc.c | 437 ++++++++++++++ hw/riscv/opentitan.c | 1 + hw/riscv/riscv_hart.c | 3 + hw/riscv/sifive_e.c | 12 +- hw/riscv/sifive_u.c | 41 +- hw/riscv/spike.c | 7 +- hw/riscv/trace-events | 7 - hw/riscv/trace.h | 1 - hw/riscv/virt.c | 9 +- hw/sd/Kconfig | 4 + hw/sd/cadence_sdhci.c | 193 ++++++ hw/sd/meson.build | 1 + hw/sd/sd.c | 2 +- hw/usb/host-libusb.c | 2 +- hw/usb/redirect.c | 2 +- include/crypto/aes.h | 4 - include/crypto/cipher.h | 4 +- include/hw/char/mchp_pfsoc_mmuart.h | 61 ++ include/hw/{riscv => char}/riscv_htif.h | 0 include/hw/{riscv => char}/sifive_uart.h | 0 include/hw/dma/sifive_pdma.h | 57 ++ include/hw/{riscv => gpio}/sifive_gpio.h | 0 include/hw/{riscv => intc}/sifive_clint.h | 4 +- include/hw/{riscv => misc}/sifive_e_prci.h | 0 include/hw/{riscv => misc}/sifive_test.h | 0 include/hw/{riscv => misc}/sifive_u_otp.h | 0 include/hw/{riscv => misc}/sifive_u_prci.h | 0 include/hw/net/cadence_gem.h | 2 + include/hw/riscv/microchip_pfsoc.h | 133 +++++ include/hw/riscv/riscv_hart.h | 1 + include/hw/riscv/sifive_e.h | 2 +- include/hw/riscv/sifive_u.h | 17 +- include/hw/sd/cadence_sdhci.h | 47 ++ include/qemu-common.h | 3 +- meson.build | 5 +- net/colo-compare.c | 18 +- net/net.c | 2 +- target/i386/kvm.c | 5 +- target/mips/translate.c | 12 +- target/riscv/cpu.c | 19 +- target/riscv/cpu.h | 8 +- target/riscv/cpu_helper.c | 8 +- target/riscv/csr.c | 4 +- tests/Makefile.include | 4 +- tests/acceptance/avocado_qemu/__init__.py | 12 + tests/benchmark-crypto-cipher.c | 12 +- tests/benchmark-crypto-hash.c | 4 +- tests/benchmark-crypto-hmac.c | 7 +- tests/meson.build | 3 +- tests/plugin/meson.build | 4 +- tests/requirements.txt | 2 +- tests/tcg/Makefile.target | 3 +- tests/test-vmstate.c | 3 - util/hexdump.c | 4 +- util/iov.c | 2 +- 120 files changed, 3410 insertions(+), 1847 deletions(-) create mode 100644 contrib/plugins/Makefile rename {tests/plugin => contrib/plugins}/hotblocks.c (100%) rename {tests/plugin => contrib/plugins}/hotpages.c (100%) rename {tests/plugin => contrib/plugins}/howvec.c (100%) rename {tests/plugin => contrib/plugins}/lockstep.c (100%) delete mode 100644 crypto/cipher-builtin.c create mode 100644 crypto/cipher-builtin.c.inc rename crypto/{cipher-gcrypt.c => cipher-gcrypt.c.inc} (52%) delete mode 100644 crypto/cipher-nettle.c create mode 100644 crypto/cipher-nettle.c.inc create mode 100644 hw/char/mchp_pfsoc_mmuart.c rename hw/{riscv => char}/riscv_htif.c (99%) rename hw/{riscv => char}/sifive_uart.c (99%) create mode 100644 hw/dma/sifive_pdma.c rename hw/{riscv => gpio}/sifive_gpio.c (99%) rename hw/{riscv => intc}/sifive_clint.c (90%) rename hw/{riscv => intc}/sifive_plic.c (99%) rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%) rename hw/{riscv => misc}/sifive_e_prci.c (99%) rename hw/{riscv => misc}/sifive_test.c (97%) rename hw/{riscv => misc}/sifive_u_otp.c (99%) rename hw/{riscv => misc}/sifive_u_prci.c (99%) create mode 100644 hw/riscv/microchip_pfsoc.c delete mode 100644 hw/riscv/trace-events delete mode 100644 hw/riscv/trace.h create mode 100644 hw/sd/cadence_sdhci.c create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h rename include/hw/{riscv => char}/riscv_htif.h (100%) rename include/hw/{riscv => char}/sifive_uart.h (100%) create mode 100644 include/hw/dma/sifive_pdma.h rename include/hw/{riscv => gpio}/sifive_gpio.h (100%) rename include/hw/{riscv => intc}/sifive_clint.h (92%) rename include/hw/{riscv => misc}/sifive_e_prci.h (100%) rename include/hw/{riscv => misc}/sifive_test.h (100%) rename include/hw/{riscv => misc}/sifive_u_otp.h (100%) rename include/hw/{riscv => misc}/sifive_u_prci.h (100%) create mode 100644 include/hw/riscv/microchip_pfsoc.h create mode 100644 include/hw/sd/cadence_sdhci.h