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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig in repository toolchain/ci/gcc.
from 0676e194c75 Revert "Fortran : ICE in build_field PR95614" adds 48e274be62b AArch64: Implement poly-type vadd intrinsics adds 11874a0d403 AArch64: Implement missing vceq*_p* intrinsics adds 6f189fa29bc AArch64: Implement missing vcls intrinsics on unsigned types adds 9f7c4bb47c9 AArch64: Implement vstrq_p128 intrinsic adds 0d27e8eb8dc AArch64: Implement vldrq_p128 intrinsic adds 23b4d65ef54 AArch64: Implement missing _p64 intrinsics for vector permutes adds 61291c4b7d4 AArch64: Implement missing vrndns_f32 intrinsic adds 803f597d312 AArch64: Implement missing p128<->f64 reinterpret intrinsics adds 3fa772a7acf testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,u [...] adds 333a4fe8434 Daily bump. adds f6d4b96180a arm: Add support for Neoverse V1 CPU
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 70 +++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-simd-builtins.def | 3 +- gcc/config/aarch64/arm_neon.h | 214 +++++++++++++++++++++ gcc/config/arm/arm-cpus.in | 10 + gcc/config/arm/arm-tables.opt | 3 + gcc/config/arm/arm-tune.md | 4 +- gcc/doc/invoke.texi | 6 +- gcc/fortran/ChangeLog | 20 ++ gcc/testsuite/ChangeLog | 89 +++++++++ .../aarch64/advsimd-intrinsics/arm-neon-ref.h | 8 +- .../aarch64/advsimd-intrinsics/vreinterpret_p128.c | 19 ++ .../aarch64/advsimd-intrinsics/vtrn_half.c | 3 - .../aarch64/advsimd-intrinsics/vuzp_half.c | 3 - .../aarch64/advsimd-intrinsics/vzip_half.c | 3 - .../gcc.target/aarch64/simd/trn_zip_p64_1.c | 44 +++++ .../gcc.target/aarch64/simd/vadd_poly_1.c | 50 +++++ .../gcc.target/aarch64/simd/vceq_poly_1.c | 29 +++ .../gcc.target/aarch64/simd/vcls_unsigned_1.c | 54 ++++++ .../gcc.target/aarch64/simd/vldrq_p128_1.c | 13 ++ .../gcc.target/aarch64/simd/vrndns_f32_1.c | 13 ++ .../gcc.target/aarch64/simd/vstrq_p128_1.c | 12 ++ 22 files changed, 653 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/trn_zip_p64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vadd_poly_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vcls_unsigned_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vldrq_p128_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vrndns_f32_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vstrq_p128_1.c