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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.
from ba45b82518 Merge tag 'bsd-user-syscall-2022q2b-pull-request' of ssh://g [...] adds 4e245a9e26 target/riscv: Remove condition guarding register zero for au [...] adds b97028b8c5 target/riscv: Set env->bins in gen_exception_illegal adds 5dacdbaeaf target/riscv: Remove generate_exception_mtval adds a9814e3e08 target/riscv: Minimize the calls to decode_save_opc adds 2e98339918 target/riscv/pmp: guard against PMP ranges with a negative size adds 562009e47c target/riscv: Fix PMU CSR predicate function adds a5a92fd6ef target/riscv: Implement PMU CSR predicate function for S-mode adds d3be1299fb target/riscv: pmu: Rename the counters extension to pmu adds 18d6d89efc target/riscv: pmu: Make number of counters configurable adds b1675eeb3e target/riscv: Implement mcountinhibit CSR adds 621f35bb2f target/riscv: Add support for hpmcounters/hpmevents adds 3780e33732 target/riscv: Support mcycle/minstret write operation adds b509caceaa target/riscv: Fixup MSECCFG minimum priv check adds be2265c776 target/riscv: Ibex: Support priv version 1.11 adds 188000952c target/riscv: Don't force update priv spec version to latest adds ec2c62dacc hw/riscv: boot: Reduce FDT address alignment constraints adds 598ca83706 target/riscv: Set minumum priv spec version for mcountinhibit adds df01af337f target/riscv: Remove CSRs that set/clear an IMSIC interrupt [...] adds 435774992e target/riscv: Update default priority table for local interrupts adds e8e86b484e Merge tag 'pull-riscv-to-apply-20220703-1' of github.com:ali [...]
No new revisions were added by this update.
Summary of changes: hw/riscv/boot.c | 4 +- target/riscv/cpu.c | 17 +- target/riscv/cpu.h | 24 +- target/riscv/cpu_bits.h | 30 +- target/riscv/cpu_helper.c | 134 ++-- target/riscv/csr.c | 857 +++++++++++++-------- target/riscv/insn_trans/trans_privileged.c.inc | 4 + target/riscv/insn_trans/trans_rvh.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 10 +- target/riscv/machine.c | 25 + target/riscv/meson.build | 3 +- target/riscv/pmp.c | 3 + target/riscv/{kvm-stub.c => pmu.c} | 16 +- target/riscv/{kvm-stub.c => pmu.h} | 22 +- target/riscv/translate.c | 31 +- tests/tcg/riscv64/Makefile.softmmu-target | 21 + tests/tcg/riscv64/issue1060.S | 53 ++ .../system/kernel.ld => riscv64/semihost.ld} | 9 +- 18 files changed, 784 insertions(+), 481 deletions(-) copy target/riscv/{kvm-stub.c => pmu.c} (62%) copy target/riscv/{kvm-stub.c => pmu.h} (61%) create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target create mode 100644 tests/tcg/riscv64/issue1060.S copy tests/tcg/{aarch64/system/kernel.ld => riscv64/semihost.ld} (64%)