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from 506313c1cd7 [ThinLTO] Fix unreachable code when parsing summary entries. new 542de76c159 [AMDGPU] gfx1010 MIMG implementation new 1c29f9f7f50 [AMDGPU] gfx1010 GCNNSAReassign pass
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Summary of changes: include/llvm/IR/IntrinsicsAMDGPU.td | 39 +- include/llvm/MC/MCInst.h | 1 + lib/Target/AMDGPU/AMDGPU.h | 3 + lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 + lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 213 ++++++++++- lib/Target/AMDGPU/CMakeLists.txt | 1 + .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 146 ++++++-- lib/Target/AMDGPU/GCNNSAReassign.cpp | 343 ++++++++++++++++++ .../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 20 +- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h | 2 + lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 24 +- lib/Target/AMDGPU/MIMGInstructions.td | 401 ++++++++++++++++----- lib/Target/AMDGPU/SIISelLowering.cpp | 79 +++- lib/Target/AMDGPU/SIInstrFormats.td | 32 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 63 +++- lib/Target/AMDGPU/SIInstrInfo.td | 1 + lib/Target/AMDGPU/SIShrinkInstructions.cpp | 100 +++++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 2 + .../CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll | 64 ++-- test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll | 20 +- test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll | 204 +++++++---- .../AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll | 8 +- .../AMDGPU/llvm.amdgcn.image.gather4.dim.ll | 56 ++- .../CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll | 11 +- test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll | 91 +++++ .../AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll | 12 +- .../CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll | 206 +++++++---- .../AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll | 21 +- .../AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll | 30 +- .../AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll | 34 +- .../AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll | 24 +- .../AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll | 49 ++- .../AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll | 27 +- .../AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll | 46 ++- test/CodeGen/AMDGPU/nsa-reassign.ll | 102 ++++++ test/MC/AMDGPU/gfx10_asm_mimg.s | 380 +++++++++++++++++++ test/MC/AMDGPU/gfx10_asm_mimg_err.s | 38 ++ test/MC/AMDGPU/mtbuf-gfx10.s | 68 ++++ test/MC/Disassembler/AMDGPU/gfx10_mimg.txt | 311 ++++++++++++++++ test/MC/Disassembler/AMDGPU/mtbuf_gfx10.txt | 69 ++++ 40 files changed, 2890 insertions(+), 466 deletions(-) create mode 100644 lib/Target/AMDGPU/GCNNSAReassign.cpp create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll create mode 100644 test/CodeGen/AMDGPU/nsa-reassign.ll create mode 100644 test/MC/AMDGPU/gfx10_asm_mimg.s create mode 100644 test/MC/AMDGPU/gfx10_asm_mimg_err.s create mode 100644 test/MC/AMDGPU/mtbuf-gfx10.s create mode 100644 test/MC/Disassembler/AMDGPU/gfx10_mimg.txt create mode 100644 test/MC/Disassembler/AMDGPU/mtbuf_gfx10.txt