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from 7fb62627cfb aarch64: testsuite: Explicitly add -mlittle-endian to vget_low_2.c new a2fd0812a54 RISC-V: Do not allow v0 as dest when merging [PR115068]. new 9781885a624 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. new af4bf422a69 RISC-V: Add vwsll combine helpers. new 309ee005aa8 RISC-V: Use widening shift for scatter/gather if applicable. new f48448276f2 RISC-V: Add vandn combine helper. new 6fa4b013543 RISC-V: Add vector popcount, clz, ctz. new 30cfdd6ff56 RISC-V: Remove dead perm series code and document.
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Summary of changes: gcc/config/riscv/autovec-opt.md | 144 ++++++++++++++++++++- gcc/config/riscv/autovec.md | 30 ++++- gcc/config/riscv/generic-vector-ooo.md | 2 +- gcc/config/riscv/riscv-v.cc | 68 +++++----- gcc/config/riscv/vector-crypto.md | 143 ++++++++++---------- gcc/config/riscv/vector.md | 100 ++++++++++---- .../gcc.target/riscv/rvv/autovec/binop/vandn-1.c | 8 ++ .../gcc.target/riscv/rvv/autovec/binop/vandn-run.c | 54 ++++++++ .../riscv/rvv/autovec/binop/vandn-template.h | 38 ++++++ .../gcc.target/riscv/rvv/autovec/binop/vwsll-1.c | 10 ++ .../gcc.target/riscv/rvv/autovec/binop/vwsll-run.c | 67 ++++++++++ .../riscv/rvv/autovec/binop/vwsll-template.h | 49 +++++++ ...ather_load_64-12.c => gather_load_64-12-zvbb.c} | 5 +- .../gcc.target/riscv/rvv/autovec/unop/clz-1.c | 8 ++ .../{partial/gimple_fold-1.c => unop/clz-run.c} | 41 +++--- .../{partial/select_vl-1.c => unop/clz-template.h} | 18 +-- .../gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 8 ++ .../{partial/gimple_fold-1.c => unop/ctz-run.c} | 43 +++--- .../{partial/select_vl-1.c => unop/ctz-template.h} | 18 +-- .../gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 4 +- .../gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 4 +- .../gcc.target/riscv/rvv/autovec/unop/popcount-3.c | 8 ++ .../riscv/rvv/autovec/unop/popcount-run-1.c | 3 +- .../select_vl-1.c => unop/popcount-template.h} | 18 +-- .../gcc.target/riscv/rvv/base/pr115068-run.c | 6 + gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c | 55 ++++++++ .../gcc.target/riscv/rvv/base/vwaddsub-1.c | 48 +++++++ gcc/testsuite/lib/target-supports.exp | 48 ++++++- 28 files changed, 816 insertions(+), 232 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h copy gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/{gather_load_64-12. [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{partial/gimple_fold-1.c => unop/c [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{partial/select_vl-1.c => unop/clz [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{partial/gimple_fold-1.c => unop/c [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{partial/select_vl-1.c => unop/ctz [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{partial/select_vl-1.c => unop/pop [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c