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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/qemu.
from c52d69e7db Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull [...] adds f448397a51 Hexagon (target/hexagon) more tcg_constant_* adds b9dd6ff91d Hexagon (target/hexagon) put writes to USR into temp until commit adds edf044c558 Merge remote-tracking branch 'remotes/quic/tags/pull-hex-202 [...] adds 1c46937358 qemu/int128: Add int128_{not,xor} adds 9276a31c34 host-utils: move checks out of divu128/divs128 adds 8ac2d6c526 host-utils: move udiv_qrnnd() to host-utils adds 40f3e79a86 host-utils: add 128-bit quotient support to divu128/divs128 adds 023462978a host-utils: add unit tests for divu128/divs128 adds b1fde411d0 tcg/optimize: Rename "mask" to "z_mask" adds 3b3f847d75 tcg/optimize: Split out OptContext adds b10f38339b tcg/optimize: Remove do_default label adds dc84988a5f tcg/optimize: Change tcg_opt_gen_{mov,movi} interface adds d0ed5151b1 tcg/optimize: Move prev_mb into OptContext adds e2577ea24f tcg/optimize: Split out init_arguments adds 8774dded02 tcg/optimize: Split out copy_propagate adds 5cf32be7d8 tcg/optimize: Split out fold_call adds ec5d4cbeef tcg/optimize: Drop nb_oargs, nb_iargs locals adds 8d57bf1e82 tcg/optimize: Change fail return for do_constant_folding_cond* adds 6b99d5bf38 tcg/optimize: Return true from tcg_opt_gen_{mov,movi} adds 137f1f4429 tcg/optimize: Split out finish_folding adds 404a148d89 tcg/optimize: Use a boolean to avoid a mass of continues adds 3eefdf2b58 tcg/optimize: Split out fold_mb, fold_qemu_{ld,st} adds 2f9f08ba43 tcg/optimize: Split out fold_const{1,2} adds bc47b1aa5b tcg/optimize: Split out fold_setcond2 adds 764d2aba08 tcg/optimize: Split out fold_brcond2 adds 079b08040e tcg/optimize: Split out fold_brcond adds c63ff55cc5 tcg/optimize: Split out fold_setcond adds 6b8ac0d149 tcg/optimize: Split out fold_mulu2_i32 adds e3f7dc2167 tcg/optimize: Split out fold_addsub2_i32 adds 0c310a3005 tcg/optimize: Split out fold_movcond adds dcd08996c9 tcg/optimize: Split out fold_extract2 adds b6617c8821 tcg/optimize: Split out fold_extract, fold_sextract adds 1b1907b846 tcg/optimize: Split out fold_deposit adds 30dd0bfeb5 tcg/optimize: Split out fold_count_zeros adds 09bacdc263 tcg/optimize: Split out fold_bswap adds 8cdb3fcb8e tcg/optimize: Split out fold_dup, fold_dup2 adds 2cfac7fa48 tcg/optimize: Split out fold_mov adds cbe42fb2f2 tcg/optimize: Split out fold_xx_to_i adds ca7bb049a0 tcg/optimize: Split out fold_xx_to_x adds e8679955ec tcg/optimize: Split out fold_xi_to_i adds 67f84c9621 tcg/optimize: Add type to OptContext adds 0e0a32bacb tcg/optimize: Split out fold_to_not adds 9caca88a76 tcg/optimize: Split out fold_sub_to_neg adds a63ce0e9cb tcg/optimize: Split out fold_xi_to_x adds da48e27202 tcg/optimize: Split out fold_ix_to_i adds fae450ba47 tcg/optimize: Split out fold_masks adds 407112b03d tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies adds 9531c078ff tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops adds 7a2f708452 tcg/optimize: Sink commutative operand swapping into fold functions adds 18cf3d07a2 tcg: Extend call args using the correct opcodes adds faa2e10045 tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values adds 4e858d96aa tcg/optimize: Use fold_xx_to_i for orc adds 5b5cf47983 tcg/optimize: Use fold_xi_to_x for mul adds 2f9d9a3422 tcg/optimize: Use fold_xi_to_x for div adds 267c17e825 tcg/optimize: Use fold_xx_to_i for rem adds 57fe5c6df2 tcg/optimize: Optimize sign extensions adds 3f2b1f8376 tcg/optimize: Propagate sign info for logical operations adds 275d7d8e70 tcg/optimize: Propagate sign info for setcond adds 2b9d0c59ed tcg/optimize: Propagate sign info for bit counting adds 93a967fbb5 tcg/optimize: Propagate sign info for shifting adds 9f660c077b softmmu: fix watchpoint processing in icount mode adds 1ab0ba8ab5 softmmu: remove useless condition in watchpoint check adds efd629fb21 softmmu: fix for "after access" watchpoints adds a92cecba27 Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-2021 [...] new 9925c8bb81 hw/riscv: virt: Don't use a macro for the PLIC configuration new bf357e1d72 hw/riscv: boot: Add a PLIC config string function new 4e8fb53c0b hw/riscv: sifive_u: Use the PLIC config helper function new 8486eb8cdc hw/riscv: microchip_pfsoc: Use the PLIC config helper function new 7d10ff8a4d hw/riscv: virt: Use the PLIC config helper function new 9b144ed444 hw/riscv: opentitan: Fixup the PLIC context addresses new 53dcea58b8 target/riscv: Add J-extension into RISC-V new 138b5c5f8f target/riscv: Add CSR defines for RISC-V PM extension new 4bbe8033fc target/riscv: Support CSRs required for RISC-V PM extension [...] new b1c279e135 target/riscv: Add J extension state description new bd5594ca28 target/riscv: Print new PM CSRs in QEMU logs new c655df7fe0 target/riscv: Support pointer masking for RISC-V for i/c/f/d [...] new 0774a7a1ff target/riscv: Implement address masking functions required f [...] new 0ee9a4e57e target/riscv: Allow experimental J-ext to be turned on new 487a99551a target/riscv: fix VS interrupts forwarding to HS new 50d1608764 target/riscv: remove force HS exception new 0e9030376e softfloat: add APIs to handle alternative sNaN propagation f [...] new 15161e425e target/riscv: change the api for RVF/RVD fmin/fmax new 6450ce5634 Merge remote-tracking branch 'remotes/alistair23/tags/pull-r [...]
The 19 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: fpu/softfloat-parts.c.inc | 25 +- fpu/softfloat.c | 19 +- hw/riscv/boot.c | 25 + hw/riscv/microchip_pfsoc.c | 14 +- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_u.c | 14 +- hw/riscv/virt.c | 20 +- include/fpu/softfloat-macros.h | 82 - include/fpu/softfloat.h | 10 + include/hw/clock.h | 5 +- include/hw/riscv/boot.h | 2 + include/hw/riscv/microchip_pfsoc.h | 1 - include/hw/riscv/sifive_u.h | 1 - include/hw/riscv/virt.h | 1 - include/qemu/host-utils.h | 121 +- include/qemu/int128.h | 20 + softmmu/physmem.c | 41 +- target/hexagon/attribs_def.h.inc | 1 + target/hexagon/gen_tcg.h | 9 +- target/hexagon/gen_tcg_funcs.py | 11 +- target/hexagon/hex_common.py | 2 + target/hexagon/macros.h | 9 +- target/hexagon/translate.c | 12 +- target/ppc/int_helper.c | 23 +- target/riscv/cpu.c | 13 + target/riscv/cpu.h | 17 +- target/riscv/cpu_bits.h | 102 +- target/riscv/cpu_helper.c | 72 +- target/riscv/csr.c | 285 +++ target/riscv/fpu_helper.c | 16 +- target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/machine.c | 27 + target/riscv/translate.c | 43 + tcg/optimize.c | 2598 ++++++++++++++--------- tcg/tcg.c | 6 +- tests/tcg/hexagon/Makefile.target | 1 + tests/tcg/hexagon/{hex_sigsegv.c => overflow.c} | 75 +- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 ++ util/host-utils.c | 137 +- 43 files changed, 2712 insertions(+), 1359 deletions(-) copy tests/tcg/hexagon/{hex_sigsegv.c => overflow.c} (56%) create mode 100644 tests/unit/test-div128.c