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from 04655110837 RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instru [...] new 39d6d4256d1 c++: Reject attributes without arguments used as pack expan [...] new d1e7f999308 aarch64: PR target/99195 annotate simple narrowing patterns [...] new e7fe650692d aarch64: Simplify QSHRN expanders and patterns
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Summary of changes: gcc/config/aarch64/aarch64-simd.md | 143 ++++----------------- gcc/cp/parser.cc | 13 +- gcc/testsuite/g++.dg/cpp0x/gen-attrs-78.C | 29 +++++ gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c | 22 +++- .../aarch64/simd/{pr99195_4.c => pr99195_5.c} | 19 ++- 5 files changed, 99 insertions(+), 127 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/gen-attrs-78.C copy gcc/testsuite/gcc.target/aarch64/simd/{pr99195_4.c => pr99195_5.c} (67%)