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from cd41085a37b rtl-ssa: Extend m_num_defs to a full unsigned int [PR108086] new 9c7e898bbd6 amdgcn: Add instruction pattern for conditional shift operations
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Summary of changes: gcc/config/gcn/gcn-valu.md | 23 +++++++++++++ gcc/testsuite/gcc.target/gcn/cond_shift_3.c | 37 +++++++++++++++++++++ .../{aarch64/sve => gcn}/cond_shift_3_run.c | 2 +- gcc/testsuite/gcc.target/gcn/cond_shift_4.c | 38 ++++++++++++++++++++++ .../{aarch64/sve => gcn}/cond_shift_4_run.c | 2 +- gcc/testsuite/gcc.target/gcn/cond_shift_8.c | 35 ++++++++++++++++++++ .../{aarch64/sve => gcn}/cond_shift_8_run.c | 2 +- gcc/testsuite/gcc.target/gcn/cond_shift_9.c | 36 ++++++++++++++++++++ .../{aarch64/sve => gcn}/cond_shift_9_run.c | 2 +- 9 files changed, 173 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_3.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_3_run.c (91%) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_4.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_4_run.c (91%) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_8.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_8_run.c (92%) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_9.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_9_run.c (92%)