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from ab2c9f7c797 AMDGPU: Stop adding m0 implicit def to SGPR spills new fdc698b7265 AMDGPU: Erase redundant redefs of m0 in SIFoldOperands new 208bbb17972 AMDGPU: Use CopyToReg for interp intrinsic lowering
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Summary of changes: lib/Target/AMDGPU/SIFoldOperands.cpp | 21 ++ lib/Target/AMDGPU/SIISelLowering.cpp | 33 +- .../AMDGPU/fold-operands-remove-m0-redef.mir | 366 +++++++++++++++++++++ test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll | 8 +- 4 files changed, 408 insertions(+), 20 deletions(-) create mode 100644 test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir