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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-project.
from 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero() adds ea399912514 [llvm-nm, llvm-objdump] Use llvm::is_contained (NFC) adds c795dd19265 [BasicAA] Pass AC/DT to isKnownNonEqual() adds 46bea9b2971 [Local] Remove unused function RemovePredecessorAndSimplify (NFC) adds e334c52addc [llvm-objcopy] Use llvm::erase_if (NFC) adds 622ea9cf74b [RISCV] Define vector widening reduction intrinsic. adds e8c7e7cdbbb [ValueTracking] Add more known non zero tests (NFC) adds b2184075127 [ValueTracking] Handle more non-trivial conditions in isKno [...] adds c7dcc4c7258 [clang-format] PR48569 clang-format fails to align case lab [...]
No new revisions were added by this update.
Summary of changes: clang/lib/Format/UnwrappedLineParser.cpp | 19 +++-- clang/unittests/Format/FormatTest.cpp | 14 ++-- llvm/include/llvm/IR/IntrinsicsRISCV.td | 6 ++ llvm/include/llvm/Transforms/Utils/Local.h | 14 ---- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 40 ++++++++++ llvm/lib/Transforms/Utils/Local.cpp | 28 ------- llvm/test/Analysis/BasicAA/sequential-gep.ll | 11 +++ llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll | 43 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll | 85 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll | 43 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll | 85 ++++++++++++++++++++ llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll | 26 +++--- llvm/test/Transforms/InstCombine/known-non-zero.ll | 92 ++++++++++++++++++++++ llvm/tools/llvm-nm/llvm-nm.cpp | 7 +- llvm/tools/llvm-objcopy/COFF/Object.cpp | 19 ++--- llvm/tools/llvm-objcopy/MachO/Object.cpp | 4 +- llvm/tools/llvm-objcopy/wasm/Object.cpp | 4 +- llvm/tools/llvm-objdump/MachODump.cpp | 4 +- 20 files changed, 454 insertions(+), 94 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll