[Tcwg-commits] [gcc] branch releases/gcc-12 updated (4a9618035a4 -> 942374058b7)

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unknown user pushed a change to branch releases/gcc-12 in repository gcc.

from 4a9618035a4 Daily bump. new 015848f7014 arm: improve vcreateq* tests new 4aa7b493027 arm: fix 'vmsr' spacing and register capitalization new 96fcd2c47ab arm: improve tests and fix vddupq* new a6cab55acb5 arm: improve tests and fix vdwdupq* new f2477c0eabb arm: improve vidupq* tests new 18c231714fd arm: improve tests and fix vdupq* new 351cc920d8a arm: improve tests and fix vcmp* new 65f3196a223 arm: improve tests for vmin* new 0aad406016e arm: improve tests for vmax* new c67e3f7b05d arm: improve tests for vabavq* new 328de4f103e arm: improve tests for vabdq* new 8aa5cd69d89 arm: improve tests and fix vabsq* new 7d3043505c7 arm: further fix overloading of MVE vaddq[_m]_n intrinsic new bbdf67595a5 arm: propagate fixed overloading of MVE intrinsic scalar pa [...] new 79431d45e2c arm: Explicitly specify other float types for _Generic over [...] new 37d0faa2aa9 arm: Add integer vector overloading of vsubq_x instrinsic new 59e6d480c2c arm: improve tests and fix vadd* new 58a9a523756 arm: improve tests for vmulq* new f47b54aaef9 arm: improve tests and fix vsubq* new c2d80e30ceb arm: improve tests for vfmasq_m* new cfc47e6e672 arm: improve tests for vhaddq_m* new b6314488b4d arm: improve tests for vhsubq_m* new 31d6b46658c arm: improve tests for viwdupq* new 4cd5d4d335d arm: improve tests for vmladavaq* new fd2b43d3ba2 arm: improve tests and fix vmlaldavaxq* new 06c2f515496 arm: improve tests for vmlasq* new aa1c6b2a3c2 arm: improve tests for vqaddq_m* new ec357ce4bce arm: improve tests for vqdmlahq_m* new 82eb1588060 arm: improve tests for vqdmul* new 374aefaae67 arm: improve tests for vqrdmlahq* new 321c5596a26 arm: improve tests for vqrdmlashq_m* new 77268ac0373 arm: improve tests for vqsubq* new 8b7e613b9d9 arm: improve tests and fix vrmlaldavhaq* new 92c75bf33c1 arm: improve tests for vrshlq* new 8baa54ba478 arm: improve tests for vsetq_lane* new 3de0d4c749f arm: Fix MVE testsuite fallouts new 51df90d7fca arm: Add missing early clobber to MVE vrev64q_m patterns new 37601980933 testsuite: [arm] Relax expected register names in MVE tests new 537b7a34462 arm: [MVE] Add missing length=8 attribute new c2dbbfbd9b1 arm: fix mve intrinsics scan body tests for C++ new 4036a318fc9 arm: improve tests and fix vclsq* new a47749ddad8 arm: improve tests and fix vclzq* new cb444c6df76 arm: improve tests and fix vnegq* new 4fdbf8cb806 arm: improve tests for vmulhq* new b821e350263 arm: improve tests for vmullbq* new 99bcb2f22e3 arm: improve tests for vmulltq* new 633a203732f arm: improve tests for vcaddq* new 455461dfccc arm: improve tests for vcmlaq* new 6171e0b1701 arm: improve tests for vcmulq* new f25c97c8326 arm: improve tests and fix vqabsq* new 9d807442910 arm: improve tests for vqdmladhq* new e776a8333ba arm: improve tests for vqdmladhxq* new 98c45781be3 arm: improve tests for vqrdmladhq* new 017b5dbc342 arm: improve tests for vqrdmladhxq* new 48afcf6f720 arm: improve tests for vqrdmlashq* new 4971715f884 arm: improve tests for vqdmlsdhq* new 997b86eda16 arm: improve tests for vqdmlsdhxq* new eae89159b54 arm: improve tests for vqrdmlsdhq* new b56b280c870 arm: improve tests for vqrdmlsdhxq* new a0cbc3d6d96 arm: improve tests for vqrdmulhq* new 856c74b2cba arm: improve tests and fix vqnegq* new af4cdaa51a3 arm: improve tests for vld2q* new fc68bca6a77 arm: fix missing extern "C" in MVE tests new c7c4dfb5989 arm: Split up MVE _Generic associations to prevent type cla [...] new 09f0fd468f5 arm: Fix vcreate definition new bb113a56e31 arm: Make MVE masked stores read memory operand [PR 108177] new 60e54b99f59 arm: fix __arm_vld1q_z* and __arm_vst1q_p* intrinsics [PR108442] new 0b968346dad arm: remove unused variables from test new d04583df6e2 arm: Mve testsuite improvements new 732102a21b7 arm: Fix vstrwq* backend + testsuite new 958a3c54645 arm: Mve backend + testsuite fixes 2 new f51bc071a57 arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSC [...] new 15fbceddeef arm: Add vorrq_n overloading into vorrq _Generic new eaae2bf98dd arm: Fix overloading of MVE scalar constant parameters on v [...] new 5d013704c80 arm: Fix MVE header pointer overloads this time (and a bit [...] new 379f99f1d7a arm testsuite: Remove reduntant tests new 8ed701b5284 arm testsuite: XFAIL or relax registers in some tests [PR109697] new 16df8b88842 arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes new 942374058b7 [arm] complete vmsr/vmrs blank and case adjustments

The 79 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/arm/arm_mve.h | 2148 +++++++++++--------- gcc/config/arm/constraints.md | 20 +- gcc/config/arm/mve.md | 285 +-- gcc/config/arm/predicates.md | 14 +- gcc/config/arm/vfp.md | 12 +- .../gcc.target/arm/acle/cde-mve-full-assembly.c | 264 +-- .../arm/mve/general/preserve_user_namespace_1.c | 6 + gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c | 21 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c | 33 +- .../gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 - .../intrinsics/mve_intrinsic_type_overloads-fp.c | 61 + .../intrinsics/mve_intrinsic_type_overloads-int.c | 98 + .../gcc.target/arm/mve/intrinsics/mve_vaddq_m.c | 48 - .../gcc.target/arm/mve/intrinsics/mve_vaddq_n.c | 31 - .../arm/mve/intrinsics/mve_vddupq_m_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vddupq_m_n_u32.c | 13 - .../arm/mve/intrinsics/mve_vddupq_m_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vddupq_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vddupq_n_u32.c | 13 - .../arm/mve/intrinsics/mve_vddupq_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vddupq_x_n_u16.c | 12 - .../arm/mve/intrinsics/mve_vddupq_x_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vddupq_x_n_u8.c | 12 - .../arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c | 13 - .../arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vidupq_m_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vidupq_m_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vidupq_m_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vidupq_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vidupq_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vidupq_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vidupq_x_n_u16.c | 12 - .../arm/mve/intrinsics/mve_vidupq_x_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vidupq_x_n_u8.c | 12 - .../arm/mve/intrinsics/mve_viwdupq_x_n_u16.c | 13 - .../arm/mve/intrinsics/mve_viwdupq_x_n_u32.c | 13 - .../arm/mve/intrinsics/mve_viwdupq_x_n_u8.c | 13 - .../mve/intrinsics/mve_vldrdq_gather_offset_s64.c | 12 - .../mve/intrinsics/mve_vldrdq_gather_offset_u64.c | 12 - .../intrinsics/mve_vldrdq_gather_offset_z_s64.c | 12 - .../intrinsics/mve_vldrdq_gather_offset_z_u64.c | 12 - .../mve_vldrdq_gather_shifted_offset_s64.c | 12 - .../mve_vldrdq_gather_shifted_offset_u64.c | 12 - .../mve_vldrdq_gather_shifted_offset_z_s64.c | 12 - .../mve_vldrdq_gather_shifted_offset_z_u64.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_f16.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_s16.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_s32.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_u16.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_u32.c | 13 - .../intrinsics/mve_vldrhq_gather_offset_z_f16.c | 12 - .../intrinsics/mve_vldrhq_gather_offset_z_s16.c | 12 - .../intrinsics/mve_vldrhq_gather_offset_z_s32.c | 12 - .../intrinsics/mve_vldrhq_gather_offset_z_u16.c | 13 - .../intrinsics/mve_vldrhq_gather_offset_z_u32.c | 13 - .../mve_vldrhq_gather_shifted_offset_f16.c | 12 - .../mve_vldrhq_gather_shifted_offset_s16.c | 13 - .../mve_vldrhq_gather_shifted_offset_s32.c | 13 - .../mve_vldrhq_gather_shifted_offset_u16.c | 13 - .../mve_vldrhq_gather_shifted_offset_u32.c | 13 - .../mve_vldrhq_gather_shifted_offset_z_f16.c | 13 - .../mve_vldrhq_gather_shifted_offset_z_s16.c | 13 - .../mve_vldrhq_gather_shifted_offset_z_s32.c | 12 - .../mve_vldrhq_gather_shifted_offset_z_u16.c | 12 - .../mve_vldrhq_gather_shifted_offset_z_u32.c | 12 - .../mve/intrinsics/mve_vldrwq_gather_offset_f32.c | 12 - .../mve/intrinsics/mve_vldrwq_gather_offset_s32.c | 13 - .../mve/intrinsics/mve_vldrwq_gather_offset_u32.c | 13 - .../intrinsics/mve_vldrwq_gather_offset_z_f32.c | 12 - .../intrinsics/mve_vldrwq_gather_offset_z_s32.c | 13 - .../intrinsics/mve_vldrwq_gather_offset_z_u32.c | 13 - .../mve_vldrwq_gather_shifted_offset_f32.c | 12 - .../mve_vldrwq_gather_shifted_offset_s32.c | 13 - .../mve_vldrwq_gather_shifted_offset_u32.c | 13 - .../mve_vldrwq_gather_shifted_offset_z_f32.c | 12 - .../mve_vldrwq_gather_shifted_offset_z_s32.c | 13 - .../mve_vldrwq_gather_shifted_offset_z_u32.c | 13 - .../intrinsics/mve_vstore_scatter_shifted_offset.c | 141 -- .../mve_vstore_scatter_shifted_offset_p.c | 142 -- .../gcc.target/arm/mve/intrinsics/sqrshr.c | 21 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 21 +- .../gcc.target/arm/mve/intrinsics/sqshl.c | 21 +- .../gcc.target/arm/mve/intrinsics/sqshll.c | 21 +- .../gcc.target/arm/mve/intrinsics/srshr.c | 21 +- .../gcc.target/arm/mve/intrinsics/srshrl.c | 21 +- .../gcc.target/arm/mve/intrinsics/uqrshl.c | 33 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 33 +- .../gcc.target/arm/mve/intrinsics/uqshl.c | 21 +- .../gcc.target/arm/mve/intrinsics/uqshll.c | 21 +- .../gcc.target/arm/mve/intrinsics/urshr.c | 35 +- .../gcc.target/arm/mve/intrinsics/urshrl.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 48 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 48 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 48 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 48 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 48 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 48 +- .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 36 +- .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 36 +- .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 36 +- .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 36 +- .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 30 +- .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 30 +- .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 28 +- .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 28 +- .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 46 +- .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 46 +- .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 66 +- .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 66 +- .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 56 +- .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 56 +- .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 32 +- .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 48 +- .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 32 +- .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 32 +- .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 30 +- .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 28 +- .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 34 +- .../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 50 +- .../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 50 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 50 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 50 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 50 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 36 +- .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 24 +- 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| 38 +- .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 34 +- .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 34 +- .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 34 +- .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 34 +- .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 33 +- .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 33 +- .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 33 +- .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 33 +- .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 24 +- .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 24 +- .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 24 +- .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 24 +- .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 17 +- .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 17 +- .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 17 +- .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 17 +- .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 17 +- .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 17 +- .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 19 +- 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+- .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 58 +- .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 58 +- .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 58 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 49 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 49 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 49 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 49 +- .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 49 +- .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 29 +- .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 29 +- .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 21 +- .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 21 +- .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 17 +- .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 31 +- 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+- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 36 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 36 +- .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 50 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 50 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 50 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 54 +- .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 50 +- .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 50 +- .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 54 +- .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 50 +- .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 50 +- .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 40 +- .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 36 +- .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 40 +- .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 36 +- .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 54 +- .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 50 +- .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 50 +- .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 58 +- .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 58 +- .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 58 +- .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 54 +- .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 54 +- .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 54 +- .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 54 +- .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 54 +- .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 54 +- .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 40 +- .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 40 +- .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 36 +- .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 44 +- .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 44 +- .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 44 +- .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 54 +- .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 54 +- .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 54 +- .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 58 +- .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 58 +- .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 58 +- .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 29 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 38 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 38 +- 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.../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 37 +- .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 37 +- .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 37 +- .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 37 +- .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 28 +- .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 28 +- .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 28 +- .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 28 +- .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 28 +- .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 28 +- .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 36 +- .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 36 +- .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 36 +- .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 36 +- .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 36 +- .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 36 +- .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 19 +- .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 19 +- .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 20 +- .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 19 +- .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 19 +- .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 20 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 25 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 25 +- .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 19 +- .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 19 +- .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 24 +- .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 24 +- .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 31 +- .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 31 +- .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 23 +- .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 23 +- .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 28 +- .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 28 +- .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 36 +- .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 36 +- .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 28 +- .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 28 +- .../vldrdq_gather_shifted_offset_z_s64.c | 36 +- .../vldrdq_gather_shifted_offset_z_u64.c | 36 +- .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 20 +- .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 28 +- .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 28 +- .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 28 +- .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 28 +- .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 28 +- .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 36 +- .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 36 +- .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 36 +- .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 36 +- .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 36 +- .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 28 +- .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 28 +- .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 28 +- .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 28 +- .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 28 +- .../vldrhq_gather_shifted_offset_z_f16.c | 36 +- .../vldrhq_gather_shifted_offset_z_s16.c | 36 +- .../vldrhq_gather_shifted_offset_z_s32.c | 36 +- .../vldrhq_gather_shifted_offset_z_u16.c | 36 +- .../vldrhq_gather_shifted_offset_z_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 20 +- .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 20 +- .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 20 +- .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 20 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 25 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 25 +- .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 18 +- .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 19 +- .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 19 +- .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 19 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 22 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 22 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 22 +- .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 28 +- .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 28 +- .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 28 +- .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 23 +- .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 23 +- .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 23 +- .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 28 +- .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 28 +- .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 28 +- .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 36 +- .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 36 +- .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 36 +- .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 28 +- .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 28 +- .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 28 +- .../vldrwq_gather_shifted_offset_z_f32.c | 36 +- .../vldrwq_gather_shifted_offset_z_s32.c | 36 +- .../vldrwq_gather_shifted_offset_z_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 18 +- .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 18 +- .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 49 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 49 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 49 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 37 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 37 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 37 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 33 +- .../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 - 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+- .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 34 +- .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 34 +- .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 34 +- .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 34 +- .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 34 +- .../arm/mve/intrinsics/vmullbq_int_s16.c | 24 +- .../arm/mve/intrinsics/vmullbq_int_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 24 +- .../arm/mve/intrinsics/vmullbq_int_u16.c | 24 +- .../arm/mve/intrinsics/vmullbq_int_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 24 +- .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 33 +- .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 33 +- .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 33 +- .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 33 +- .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 33 +- .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 33 +- .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 34 +- .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 34 +- 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| 34 +- .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 30 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 30 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 30 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 32 +- .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 33 +- 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| 33 +- .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 28 +- .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 30 +- .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 28 +- .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 28 +- .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 28 +- .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 30 +- .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 30 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 33 +- .../{vcreateq_f16.c => vrev64q_m_s16-clobber.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 24 +- 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