This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/llvm-project.
from 4065e92195b Upgrade some instances of std::sort to llvm::sort. NFC. adds ced0d1f42b3 [BPF] support 128bit int explicitly in layout spec adds 2d24d74b859 [AMDGPU] Stabilize sort order adds d3b6e1f1f93 [ADT] Automatically forward llvm::sort to array_pod_sort if safe adds 97cc1275c7d [InstCombine] Merge two functions; NFC adds 2215dcf1d75 [InstCombine] Remove unreachable blocks before DCE adds ba2e72c54ec [MDBuilder] Don't use stable sort for sorting integers. adds b578f130a72 [COFF] Stabilize sort adds dd030036f0a Put back initializers that were dropped in 0ab5b5b8581d9f29 [...] adds 9564f46766f AMDGPU: Make use of default operands adds 09d40218539 Fix compatibility for __builtin_stdarg_start adds fc93787d7e8 [MC][PowerPC] Make .reloc support arbitrary relocation types adds c0aa97b6327 [X86] Add cost model test cases for fmin/fmax reduction. adds 4bf015c035e [AlignmentFromAssumptions] Fix a SCEV assertion resulting f [...] adds 6dab8067123 [mlir] Add exp2 conversion to llvm.intr.exp2 adds a7115d51be0 [X86] X86CallFrameOptimization - generalize slow push code path adds 6ba63510720 [PostOrderIterator] Use SmallVector to store stack; NFC adds 49d00824bbb [VPlan] Use one VPWidenRecipe per original IR instruction. (NFC). adds b632bd88a63 [mlir] NFC: fix trivial typo in documents adds 10439f9e32e [X86][AVX] Add X86ISD::VALIGN target shuffle decode support adds da4c7db793a [X86] Rename matchShuffleAsByteRotate to matchShuffleAsElem [...] adds 7734e4b3a36 [X86][AVX] Combine 128-bit lane shuffles with a zeroable up [...] adds 1e363023b82 [InstCombine] Use replaceOperand() in a few more places adds 6f07a9e80ab [InstCombine] Erase original add when creating saddo adds 28f67bd5c56 [InstCombine] Fix worklist management in varargs transform adds 99913ef3d14 [OpenMP] set_bits iterator yields unsigned elements, no ref [...] adds 26fa33755f1 [InstCombine] Simplify select of cmpxchg transform adds b44f07045c5 Remove unnecessary empty comments from test check lines. NFC. adds 443dcc0e008 [X86][AVX] Add tests for 512-bit shuffle patterns that coul [...] new febcb24f149 [InstCombine] make test independent of branch undef/UB; NFC new fc3cc8a4b07 [VectorCombine] skip debug intrinsics first for efficiency new 97bbe7ad2a9 AMDGPU: Fix typo new 0b68ca51623 AMDGPU: Add some additional tests for v_cvt_ubyte* formation new ab7a41069eb AMDGPU: Fix using wrong instruction for FP conversion new d15723ef065 AMDGPU/GlobalISel: Remove redundant virtual new cce3d96bcc6 GlobalISel: Add matcher for G_SHL new c0955edfd6e Introduce support for lib function aligned_alloc in TLI / m [...] new a9ddcd6411b [InstCombine] Erase old add when optimizing add overflow
The 9 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang/include/clang/Basic/Builtins.def | 2 +- clang/lib/Basic/Targets/BPF.h | 4 +- clang/test/CodeGen/target-data.c | 4 +- clang/test/SemaCXX/vararg-non-pod.cpp | 7 + lld/COFF/PDB.cpp | 2 + llvm/include/llvm/ADT/PostOrderIterator.h | 3 +- llvm/include/llvm/ADT/STLExtras.h | 22 +- llvm/include/llvm/Analysis/MemoryBuiltins.h | 8 + llvm/include/llvm/Analysis/TargetLibraryInfo.def | 3 + .../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 6 + llvm/include/llvm/Target/TargetOptions.h | 2 + llvm/lib/Analysis/BasicAliasAnalysis.cpp | 2 +- llvm/lib/Analysis/MemoryBuiltins.cpp | 26 +- llvm/lib/Analysis/TargetLibraryInfo.cpp | 2 + llvm/lib/Frontend/OpenMP/OMPContext.cpp | 16 +- llvm/lib/IR/MDBuilder.cpp | 2 +- .../Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 4 +- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp | 6 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 +- llvm/lib/Target/AMDGPU/SIISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 46 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 4 +- llvm/lib/Target/BPF/BPFTargetMachine.cpp | 4 +- .../Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 47 +- .../PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp | 6 +- llvm/lib/Target/X86/X86CallFrameOptimization.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 43 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 11 +- .../Transforms/InstCombine/InstCombineInternal.h | 6 + .../InstCombine/InstCombineMulDivRem.cpp | 24 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 30 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 4 +- .../InstCombine/InstructionCombining.cpp | 60 +-- .../Transforms/Scalar/AlignmentFromAssumptions.cpp | 5 + llvm/lib/Transforms/Utils/BuildLibCalls.cpp | 4 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 17 +- llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h | 5 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 3 +- llvm/lib/Transforms/Vectorize/VPlan.h | 25 +- llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp | 15 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/Analysis/CostModel/X86/reduce-fmax.ll | 110 +++++ llvm/test/Analysis/CostModel/X86/reduce-fmin.ll | 110 +++++ llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 380 +++++++++++++- llvm/test/CodeGen/BPF/i128.ll | 67 +++ llvm/test/CodeGen/X86/atomic-idempotent.ll | 547 ++++++++++++++++----- llvm/test/CodeGen/X86/avx-vperm2x128.ll | 10 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 84 ++-- llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll | 17 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 17 +- llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll | 211 ++++---- .../CodeGen/X86/vector-shuffle-combining-avx2.ll | 45 +- llvm/test/CodeGen/X86/vector-shuffle-v1.ll | 10 +- llvm/test/MC/PowerPC/ppc32-reloc-directive.s | 9 + llvm/test/MC/PowerPC/ppc64-reloc-directive.s | 9 + .../AlignmentFromAssumptions/amdgpu-crash.ll | 33 ++ .../test/Transforms/DeadStoreElimination/simple.ll | 13 + .../InstCombine/pr33689_same_bitwidth.ll | 6 +- llvm/unittests/Analysis/TargetLibraryInfoTest.cpp | 1 + .../CodeGen/GlobalISel/PatternMatchTest.cpp | 8 + .../Transforms/Vectorize/VPlanHCFGTest.cpp | 26 +- mlir/docs/ConversionToLLVMDialect.md | 2 +- mlir/docs/CreatingADialect.md | 2 +- mlir/docs/Diagnostics.md | 4 +- mlir/docs/OpDefinitions.md | 2 +- mlir/docs/RationaleLinalgDialect.md | 2 +- mlir/include/mlir/Dialect/GPU/GPUOps.td | 2 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 3 +- .../mlir/Dialect/Linalg/IR/LinalgStructuredOps.td | 2 +- .../Linalg/IR/LinalgStructuredOpsInterface.td | 13 +- mlir/include/mlir/Dialect/Quant/QuantOps.td | 4 +- mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 2 +- mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td | 2 +- mlir/include/mlir/Dialect/StandardOps/IR/Ops.td | 8 + mlir/include/mlir/Dialect/Vector/VectorOps.td | 4 +- .../mlir/Interfaces/InferTypeOpInterface.td | 3 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 2 + .../StandardToLLVM/convert-to-llvmir.mlir | 22 +- .../StandardToSPIRV/std-types-to-spirv.mlir | 2 +- mlir/test/IR/attribute.mlir | 2 +- mlir/test/Target/llvmir-intrinsics.mlir | 9 + mlir/test/mlir-tblgen/llvm-intrinsics.td | 2 +- 83 files changed, 1728 insertions(+), 579 deletions(-) create mode 100644 llvm/test/Analysis/CostModel/X86/reduce-fmax.ll create mode 100644 llvm/test/Analysis/CostModel/X86/reduce-fmin.ll create mode 100644 llvm/test/CodeGen/BPF/i128.ll create mode 100644 llvm/test/Transforms/AlignmentFromAssumptions/amdgpu-crash.ll