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from 906fd9ab476 [AArch64] Support reserving x1-7 registers. new 4e9fc1ef01f [WebAssembly] Change SIMD lane indices to vec_i8imm_op new a5f1bd02178 [InstCombine] narrow vector select with padded condition an [...]
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Summary of changes: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 8 ++-- .../InstCombine/InstCombineVectorOps.cpp | 38 ++++++++++++++++++ .../InstCombine/shuffle-select-narrow.ll | 46 +++++++++++----------- 3 files changed, 66 insertions(+), 26 deletions(-)