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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/llvm-monorepo.
from a1ac7be38f4 [X86] Add optsize SHLD/SHRD tests adds cdba30f1079 [X86] Lower to SHLD/SHRD on slow machines for optsize adds ec357d47d9f [X86] Begin cleaning up combineOr -> SHLD/SHRD. NFCI. adds abb46c15d95 [X86] Autogenerate complete checks. NFC adds 8a96b47e9c1 Fix a lit test failure after MallocChecker changes adds 9214bf699fb [gn build] Add build files for llvm-as, llvm-dis, llvm-dwar [...] adds 72a03279e15 [gn build] Add build files for obj2yaml, yaml2obj, and lib/ [...] adds 3ab128977a0 [gn build] Merge r349167 adds c20c3d2c429 [regex] Use distinct __regex_word on NetBSD adds c58dea983a2 [test] [ctime] Ignore -Wformat-zero-length warnings adds 3d538d8f435 Expand TSan sysroot workaround to NetBSD adds 9e93e900222 Improve the comment in previous adds 364a2879439 [X86] Add computeKnownBits tests for funnel shift intrinsics adds ccdeb3ae676 [SelectionDAG] Add FSHL/FSHR support to computeKnownBits adds fc047bd52c9 Document the usage of BOOTSTRAP_XXX with stage2 builds adds cdeccdb1394 Thread safety analysis: Allow scoped releasing of capabilities adds 38f18781abf Use backquotes to avoid a sphinx unexpected error: Unknown [...] adds 7960e9deae3 Update the list of platforms & archs adds cdf8dacfbb3 [DAGCombiner] allow hoisting vector bitwise logic ahead of [...] adds 7eb68c699a8 [x86] increment/decrement constant vector with min/max in v [...] adds ae0f1fca64d [test] [support] Use socket()+bind() to create unix sockets [...] adds 7543f21ff70 [InstCombine] add tests for vector widening transforms (PR4 [...] adds 7c250e6aa1b [InstCombine] regenerate test checks; NFC adds da1f4f8ceb2 Thread safety analysis: Avoid intermediate copies [NFC] adds f8ddec3c1fe [InstCombine] Add additional saturating add/sub + icmp tests; NFC adds 42a68c9adac [InstCombined] Add more tests for cttz/ctlz + icmp; NFC adds 2218c1a36d2 [InstCombine] Regenerate test checks; NFC adds 364b4121bf4 Revert "[InstCombine] Regenerate test checks; NFC" adds 4d716e0786b Clarify a few minor details. adds 922b1395dfc [X86] Autogenerate complete checks. NFC adds 1235cfe7c12 [X86] Remove truncation handling from EmitTest. Replace it [...] adds e9c3495a0ea Add a description of the similar packets defined in the gdb [...] adds 91c3f1a83c6 Regenerate test (merges X86+X64 cases). NFCI. adds a8930e2a29c [InstCombine] Make cttz/ctlz knownbits tests more robust; NFC
No new revisions were added by this update.
Summary of changes: .../test/clang-tidy/static-analyzer.cpp | 2 +- clang/lib/Analysis/ThreadSafety.cpp | 144 ++-- clang/test/SemaCXX/warn-thread-safety-analysis.cpp | 104 +++ compiler-rt/lib/tsan/CMakeLists.txt | 11 +- libcxx/include/regex | 4 + .../std/utilities/time/date.time/ctime.pass.cpp | 4 + .../test/support/filesystem_dynamic_test_helper.py | 10 +- lldb/docs/lldb-platform-packets.txt | 36 +- llvm/RELEASE_TESTERS.TXT | 4 +- llvm/docs/AdvancedBuilds.rst | 9 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 13 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 33 + llvm/lib/Target/X86/X86ISelLowering.cpp | 190 +++-- llvm/test/CodeGen/ARM/setcc-logic.ll | 3 +- .../CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll | 18 +- .../CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll | 18 +- llvm/test/CodeGen/X86/avx512-select.ll | 24 +- llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll | 19 +- llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll | 109 ++- llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll | 52 +- llvm/test/CodeGen/X86/fold-load.ll | 43 +- llvm/test/CodeGen/X86/fshl.ll | 53 +- llvm/test/CodeGen/X86/fshr.ll | 53 +- llvm/test/CodeGen/X86/known-bits.ll | 33 + llvm/test/CodeGen/X86/pr34137.ll | 9 +- llvm/test/CodeGen/X86/psubus.ll | 44 +- llvm/test/CodeGen/X86/sat-add.ll | 6 +- llvm/test/CodeGen/X86/test-shrink-bug.ll | 2 +- llvm/test/CodeGen/X86/vec_minmax_match.ll | 11 +- llvm/test/CodeGen/X86/vec_setcc-2.ll | 94 +-- llvm/test/CodeGen/X86/vector-rotate-128.ll | 28 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 24 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 12 +- llvm/test/CodeGen/X86/xop-intrinsics-fast-isel.ll | 859 +++++++-------------- llvm/test/CodeGen/X86/zext-logicop-shift-load.ll | 68 +- llvm/test/Transforms/InstCombine/cast.ll | 691 ++++++++--------- llvm/test/Transforms/InstCombine/cmp-intrinsic.ll | 155 +++- llvm/test/Transforms/InstCombine/intrinsics.ll | 32 +- llvm/test/Transforms/InstCombine/select-bitext.ll | 196 ++--- llvm/test/Transforms/InstCombine/vector-casts.ll | 32 + .../Transforms/InstSimplify/saturating-add-sub.ll | 145 +++- llvm/utils/gn/secondary/BUILD.gn | 9 + .../secondary/llvm/lib/CodeGen/GlobalISel/BUILD.gn | 1 + .../gn/secondary/llvm/lib/ObjectYAML/BUILD.gn | 22 + .../utils/gn/secondary/llvm/tools/llvm-as/BUILD.gn | 11 + .../gn/secondary/llvm/tools/llvm-dis/BUILD.gn | 10 + .../secondary/llvm/tools/llvm-dwarfdump/BUILD.gn | 14 + .../utils/gn/secondary/llvm/tools/llvm-mc/BUILD.gn | 16 + .../gn/secondary/llvm/tools/obj2yaml/BUILD.gn | 18 + .../gn/secondary/llvm/tools/yaml2obj/BUILD.gn | 16 + .../gn/secondary/llvm/utils/FileCheck/BUILD.gn | 8 + llvm/utils/gn/secondary/llvm/utils/count/BUILD.gn | 5 + llvm/utils/gn/secondary/llvm/utils/not/BUILD.gn | 8 + 53 files changed, 1932 insertions(+), 1603 deletions(-) create mode 100644 llvm/utils/gn/secondary/llvm/lib/ObjectYAML/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-as/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-dis/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-dwarfdump/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-mc/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/obj2yaml/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/yaml2obj/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/utils/FileCheck/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/utils/count/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/utils/not/BUILD.gn