[Tcwg-commits] [binutils-gdb] branch master updated (1d5d29e73f4 -> 69b1ffdb011)

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from 1d5d29e73f4 gdb: Catch exceptions if the source file is not found new 69b1ffdb011 sim/aarch64: Fix register ordering bug in blr (PR sim/25318)

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Summary of changes: sim/aarch64/ChangeLog | 6 ++++++ sim/aarch64/simulator.c | 7 +++---- 2 files changed, 9 insertions(+), 4 deletions(-)