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from a36486e33b2 [LV] Model masking in VPlan, introducing VPInstructions new aeb7444c9bd AMDGPU: Partial ILP scheduler port from SelectionDAG to Sch [...] new b2ea712e111 [AArch64][TableGen] Skip tied result operands for InstAlias new 14f881da7f9 [PPC] Heuristic to choose between a X-Form VSX ld/st vs a X [...]
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Summary of changes: lib/Target/AArch64/AArch64InstrInfo.td | 32 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 + lib/Target/AMDGPU/CMakeLists.txt | 1 + lib/Target/AMDGPU/GCNILPSched.cpp | 364 +++++++++++++++++++++ lib/Target/AMDGPU/GCNIterativeScheduler.cpp | 51 ++- lib/Target/AMDGPU/GCNIterativeScheduler.h | 4 +- lib/Target/PowerPC/P9InstrResources.td | 13 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 107 ++++-- lib/Target/PowerPC/PPCInstrInfo.h | 3 + lib/Target/PowerPC/PPCInstrVSX.td | 79 +++-- lib/Target/PowerPC/PPCVSXSwapRemoval.cpp | 2 + test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll | 4 +- test/CodeGen/AArch64/arm64-build-vector.ll | 10 +- test/CodeGen/AArch64/arm64-dup.ll | 10 +- test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll | 2 +- test/CodeGen/AArch64/arm64-neon-copy.ll | 106 +++--- test/CodeGen/AArch64/arm64-smaxv.ll | 12 +- test/CodeGen/AArch64/arm64-sminv.ll | 12 +- test/CodeGen/AArch64/arm64-stp.ll | 12 +- test/CodeGen/AArch64/arm64-umaxv.ll | 12 +- test/CodeGen/AArch64/arm64-uminv.ll | 12 +- test/CodeGen/AArch64/arm64-vaddv.ll | 28 +- test/CodeGen/AArch64/arm64-vcombine.ll | 2 +- test/CodeGen/AArch64/arm64-vector-insertion.ll | 4 +- test/CodeGen/AArch64/bitreverse.ll | 2 +- .../AArch64/concat_vector-scalar-combine.ll | 26 +- test/CodeGen/AArch64/fp16-v16-instructions.ll | 16 +- test/CodeGen/AArch64/fp16-v4-instructions.ll | 40 +-- test/CodeGen/AArch64/fp16-v8-instructions.ll | 41 +-- test/CodeGen/AArch64/fp16-vector-shuffle.ll | 14 +- test/CodeGen/AArch64/vector-fcopysign.ll | 6 +- ...hedule-regpressure-limit.ll => schedule-ilp.ll} | 14 +- test/CodeGen/PowerPC/VSX-XForm-Scalars.ll | 45 +++ test/CodeGen/PowerPC/build-vector-tests.ll | 72 ++-- test/CodeGen/PowerPC/direct-move-profit.ll | 4 +- test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll | 4 +- test/CodeGen/PowerPC/ppc64le-smallarg.ll | 4 +- test/CodeGen/PowerPC/pr25157-peephole.ll | 2 +- test/CodeGen/PowerPC/pr25157.ll | 2 +- test/CodeGen/PowerPC/select-addrRegRegOnly.ll | 2 +- test/CodeGen/PowerPC/select_const.ll | 2 +- test/CodeGen/PowerPC/vsx_insert_extract_le.ll | 8 +- test/CodeGen/PowerPC/vsx_scalar_ld_st.ll | 20 +- test/MC/AArch64/arm64-advsimd.s | 64 ++-- test/MC/Disassembler/AArch64/arm64-advsimd.txt | 48 +-- utils/TableGen/AsmWriterEmitter.cpp | 17 +- 46 files changed, 971 insertions(+), 379 deletions(-) create mode 100644 lib/Target/AMDGPU/GCNILPSched.cpp copy test/CodeGen/AMDGPU/{schedule-regpressure-limit.ll => schedule-ilp.ll} (98%) create mode 100644 test/CodeGen/PowerPC/VSX-XForm-Scalars.ll